8.3.3 WDO Output

The TPS3435 device offers WDO output pin. WDO output is asserted when MR pin voltage is lower than 0.3 X

VDD or watchdog timer error is detected.

The output will be asserted for tWDO time when any relevant events described above are detected, except for MR

event. The time tWDO can be programmed by connecting a capacitor between CRST pin and GND or device will

assert tWDO for fixed time duration as selected by orderable part number. Refer Section 5 section for all available

options.

Equation 2 describes the relationship between capacitor value and the time tWDO. Ensure the capacitance meets

the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation

of the device.

tWDO (sec) = 4.95 x 106 x CCRST (F)

(2)

TPS3435 also offers a unique option of latched output. An orderable with latched output will hold the output in

asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is

latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD

level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative

edge is detected or the device is shutdown and powered up again.

8.4 Device Functional Modes

Table 8-3 summarizes the functional modes of the TPS3435.

Table 8-3. Device Functional Modes

VDD

Watchdog Status

WDI

WDO

VDD < VPOR

Not Applicable

—

Undefined

VPOR ≤ VDD < VDDmin

Not Applicable

Ignored

High

VDD ≥ VDDmin

Disabled

Ignored

High

Enabled

tpulse (1) < tWD(min)

High

Enabled

tpulse (1) > tWD(max)

Low

(1)

Where tpulse is the time between falling edges on WDI.

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TPS3435

SNVSCF7 – DECEMBER 2022

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