UPSD3422_V01 datasheet(215/300 Pages) STMICROELECTRONICS

215 / 300 page

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

PSD module

215/300

Bit (DQ5) indicates a time-out condition on the Erase cycle, a ’0’ indicates no error. The

8032 can read any location within the sector being erased to get the Toggle Flag Bit (DQ6)

and the Error Flag Bit (DQ5).

PSDsoft Express generates ANSI C code functions the user may use to implement these

Data Toggling algorithms.

Figure 72.

Data toggle flowchart

28.5.13

Ready/Busy (PC3)

This signal can be used to output the Ready/Busy status of a program or erase operation on

either Flash memory. The output on the Ready/Busy pin is a ’0’ (Busy) when either Flash

memory array is being written, or when either Flash memory array is being erased. The

output is a ’1’ (Ready) when no program or erase operation is in progress. To activate this

function on this pin, the user must select the “Ready/Busy” selection in PSDsoft Express

when configuring pin PC3. This pin may be polled by the 8032 or used as a 8032 interrupt to

indicate when an erase or program operation is complete (requires routing the signal on PC

board from PC3 back into a pin on the MCU module). This signal is also available internally

on the PSD module as an input to both PLDs (without routing a signal externally on PC

board) and its signal name is “rd_bsy”. The Ready/Busy output can be probed during lab

development to check the timing of Flash memory programming in the system at run-time.

28.5.14

Bypassed unlock sequence

The Bypass Unlock mode allows the 8032 to program bytes in the Flash memories faster

than using the standard Flash program instruction sequences because the typical AAh, 55h

unlock bus cycles are bypassed for each byte that is programmed. Bypassing the unlock

READ

DQ5 & DQ6

START

READ DQ6

FAIL

PASS

AI01370B

DQ6

TOGGLE

YES

DQ5

= 1

YES

DQ6

TOGGLE

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