UPSD3422_V01 datasheet(219/300 Pages) STMICROELECTRONICS

219 / 300 page

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memory contents through its 8-bit data bus even while the security bit is set. The 8032 can

read the status of the security bit at run-time (but it cannot change it) by reading the csiop

28.5.25

PLDs

The PSD module contains two PLDs: the Decode PLD (DPLD), and the General PLD

(GPLD), as shown in Figure 73 on page 221. Both PLDs are fed by a common PLD input

signal bus, and additionally, the GPLD is connected to the 8032 data bus.

PLD logic is specified using PSDsoft Express and programmed into the PSD module using

the JTAG ISP channel. PLD logic is non-volatile and available at power-up. PLDs may not be

programmed by the 8032. The PLDs have selectable levels of performance and power

consumption.

The DPLD performs address decoding, and generates select signals for internal and

external components, such as memory, registers, and I/O ports. The DPLD can generate

External Chip-Select (ECS1-ECS2) signals on Port D.

The GPLD can be used for logic functions, such as loadable counters and shift registers,

state machines, encoding and decoding logic. These logic functions can be constructed

from a combination of 16 Output Macrocells (OMC), 20 Input Macrocells (IMC), and the

AND-OR Array.

Routing of the 16 OMCs outputs can be divided between pins on three Ports A, B, or C by

the OMC Allocator as shown in Figure 77 on page 227. Eight of the 16 OMCs that can be

routed to pins on Port A or Port B and are named MCELLAB0-MCELLAB7. The other eight

OMCs to be routed to pins on Port B or Port C and are named MCELLBC0-MCELLBC7.

This routing depends on the pin number assignments that are specified in PSDsoft Express

for “PLD Outputs” in the Pin Definition section. OMC outputs can also be routed internally

(not to pins) used as buried nodes to create shifters, counters, etc.

The AND-OR Array is used to form product terms. These product terms are configured from

the logic definitions entered in PSDsoft Express. A PLD Input Bus consisting of 69 signals is

connected to both PLDs. Input signals are shown in Table 167, both the true and

compliment versions of each of these signals are available at inputs to each PLD.

Table 165.

Main Flash memory protection register definition (address = csiop +

offset C0h)(1)

Bit definitions:

Sec_Prot 1 = Flash memory sector is write protected, 0 = Flash memory sector is not write

protected.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Sec7_Prot

Sec6_Prot

Sec5_Prot

Sec4_Prot

Sec3_Prot

Sec2_Prot

Sec1_Prot

Sec0_Prot

Table 166.

Secondary Flash memory protection/security register definition (csiop +

offset C2h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3(1)

Sec_Prot 1 = Flash memory sector is write protected, 0 = Flash memory sector is not write

protected.

Bit 2(1)

Bit 1(1)

Bit 0(1)

Security_Bit

(2)

Security_Bit = 1, device is secured, 0 = not secured.

not used

Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot

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UPSD3422 Datasheet(PDF) 219 Page - STMicroelectronics

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