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UPSD3422 Datasheet(PDF) 220 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 220 Page - STMicroelectronics |
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220 / 300 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD module UPSD3422, UPSD3433, UPSD3434, UPSD3454 220/300 Note: The 8032 data bus, D0 - D7, does not route directly to PLD inputs. Instead, the 8032 data bus has indirect access to the GPLD (not the DPLD) when the 8032 reads and writes the OMC and IMC registers within csiop address space. 28.5.26 Turbo bit and PLDs The PLDs can minimize power consumption by going to standby after ALL the PLD inputs remain unchanged for an extended time (about 70ns). When the Turbo Bit is set to logic one (Bit 3 of the csiop PMMR0 register), Turbo mode is turned off and then this automatic standby mode is achieved. Turning off Turbo mode increases propagation delays while reducing power consumption. The default state of the Turbo Bit is logic zero, meaning Turbo mode is on. Additionally, four bits are available in the csiop PMMR0 and PMMR2 registers to block the 8032 bus control signals (RD, WR, PSEN, ALE) from entering the PLDs. This reduces power consumption and can be used only when these 8032 control signals are not used in PLD logic equations. See Section 28.5.52: Power management on page 248. Table 167. DPLD and GPLD inputs Input source Input name Number of signals 8032 address bus A0-A15 16 8032 bus control signals PSEN, RD, WR, ALE 4 Reset from MCU module RESET 1 Power-Down from Auto-Power Down counter PDN 1 PortA input macrocells (80-pin devices only) PA0-PA7 8 PortB input macrocells PB0-PB7 8 PortC input macrocells PC2, PC3, PC4, PC7 4 Port D inputs (52-pin devices have only PD1) PD1, PD2 2 Page register PGR0-PGR7 8 Macrocell OMC bank AB Feedback MCELLAB FB0-7 8 Macrocell OMC bank BC Feedback MCELLBC FB0-7 8 Flash memory status bit Ready/Busy 1 Obsolete Product(s) - Obsolete Product(s) |
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