UPSD3422_V01 datasheet(218/300 Pages) STMICROELECTRONICS

218 / 300 page

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28.5.20

Reset Flash

The Reset Flash instruction sequence resets the embedded algorithm running on the state

machine in the targeted Flash memory (Main or Secondary) and the memory goes into

Read Array mode. The Reset Flash instruction consists of one bus WRITE cycle as shown

in Table 163 on page 209, and it must be executed after any error condition that has

occurred during a Flash memory Program or Erase operation.

It may take the Flash memory up to 25µs to complete the Reset cycle. The Reset Flash

instruction sequence is ignored when it is issued during a Program or Bulk Erase operation.

The Reset Flash instruction sequence aborts any on-going Sector Erase operation and

returns the Flash memory to Read Array mode within 25µs.

28.5.21

Reset signal applied to Flash memory

Whenever the PSD module receives a reset signal from the MCU module, any operation

that is occurring in either Flash memory array will be aborted and the array(s) will go to

Read Array mode. It may take up to 25µs to abort an operation and achieve Read Array

mode.

A reset from the MCU module will result from any of these events: an active signal on the

UPSD34xx RESET_IN input pin, a watchdog timer time-out, detection of low VCC, or a JTAG

debug channel reset event.

28.5.22

Flash memory sector protection

Each Flash memory sector can be separately protected against program and erase

operations. This mode can be activated (or deactivated) by selecting this feature in PSDsoft

Express and then programming through the JTAG Port. Sector protection can be selected

for individual sectors, and the 8032 cannot override the protection during run-time. The 8032

can read, but not change, sector protection.

Any attempt to program or erase a protected Flash memory sector is ignored. The 8032 may

read the contents of a Flash sector even when a sector is protected.

Sector protection status is not read using Flash memory instruction sequences, but instead

this status is read by the 8032 reading two registers within csiop address space shown in

Table 165 and Table 166.

28.5.23

Flash memory protection during power-up

Flash memory WRITE operations are automatically prevented while VDD is ramping up until

it rises above VLKO voltage threshold at which time Flash memory WRITE operations are

allowed.

28.5.24

PSD module security bit

A programmable security bit in the PSD module protects its contents from unauthorized

viewing and copying. The security bit is set using PSDsoft Express and programmed into

the PSD module with JTAG. When set, the security bit will block access of JTAG

programming equipment from reading or modifying the PSD module Flash memory and

PLD configuration. The security bit also blocks JTAG access to the MCU module for

debugging. The only way to defeat the security bit is to erase the entire PSD module using

JTAG (erase is the only JTAG operation allowed while security bit is set), after which the

device is blank and may be used again. The 8032 MCU will always have access to Flash

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UPSD3422 Datasheet(PDF) 218 Page - STMicroelectronics

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