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MB90F474LPF Datasheet(PDF) 71 Page - fujitsu semiconductor |
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MB90F474LPF Datasheet(HTML) 71 Page - fujitsu semiconductor |
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71 / 118 page  MB90470 Series 71 (2) Block Diagram SCM HCLK SCLK MCM WS1 WS0 SCS MCS CS1 CS0 STP SLP SPL RST TMD CG1 CG0 2 2 X0A X1A RST pin pin pin pin pin X0 X1 MCLK Standby control circuit Low power mode control register (LPMCR) Pin High-Z control circuit Internal reset generator circuit CPU clock control circuit Peripheral clock control circuit Pin high-impedance control Internal reset CPU clock Peripheral clock Stop, sleep signals Stop signal CPU intermittent operation selector Standby control circuit Intermittent cycle selection Interrupt release Machine clock Clock generator module Oscillator stabilization wait release Clock selector Oscillator stabilization wait period selector Divide by 4 PLL multiplier circuit Sub-clock generator circuit Clock select register (CKSCR) System clock generator circuit Divide by 2 Divide 1024 Divide by 2 Divide by 4 Divide by 4 Divide by 4 Divide by 2 Time base timer To watchdog timer Re- served HCLK : Oscillator clock MCLK : Main clock SCLK : Sub-clock |
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