MB90F474LPF datasheet(19/118 Pages) FUJITSU

19 / 118 page

MB90470 Series

s BLOCK DIAGRAM

P00 to P07 (8 pins) : Input pull-up resistance setting register provided.

P10 to P17 (8 pins) : Input pull-up resistance setting register provided.

P40 to P47 (8 pins) : Open drain setting register provided.

P70 to P75 (6 pins) : Open drain setting register provided.

P76, P77 (2 pins)

: Open drain

Note : In the above diagram, I/O ports are shown sharing pin numbers with the built-in function blocks. However

pins may not be used as I/O ports when they are in use as pins for build-in function modules.

RAM

Clock

control circuit

P00

P07

P10

P17

P20

P27

P30

P37

P40

P47

P50

P57

P60

P67

P70

P77

P80

P87

ROM

µDMA

Communication prescaler

UART

I/O expansion serial

interface

× 2 channels

A/D converter

(10-bit)

IN0, IN1

OUT0, OUT1,

OUT2, OUT3,

OUT4, OUT5

P90

P97

CS0, CS1,

CS2, CS3

PA0

PA3

X0, X1, RST

X0A, X1A

MD2, MD1, MD0

SIN0

SOT0

SCK0

SIN1, SIN2

SOT1, SOT 2

SCK1, SCK2

AVCC

AVRH

AVSS

ADTG

AN0 to AN7

AIN0, AIN1

BIN0, BIN1

ZIN0, ZIN1

PWC0

PWC1

PWC2

PPG0, PPG1

PPG2, PPG3

PPG4, PPG5

IRQ0 to IRQ7

EXTC

MT00

MT01

TIN0

TOT0

SCL

SDA

µPG

Chip select

16-bit reload timer

I2C interface

External interrupt

I/O ports

Input/output timer

16-bit input capture

× 2

16-bit output compare

× 6

16-bit free-run timer

CPU

FMC-16LX

series core

Interrupt controller

8/16-bit PPG

8/16-bit

up/down counter

16-bit PWC

3 channels

MB90F474LPF Datasheet(PDF) 19 Page - fujitsu semiconductor

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