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STM32C011F6U6 Datasheet(PDF) 68 Page - STMicroelectronics |
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STM32C011F6U6 Datasheet(HTML) 68 Page - STMicroelectronics |
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68 / 94 page ![]() Electrical characteristics STM32C011x4/x6 68/94 DS13866 Rev 3 tSTAB ADC power-up time LDO already started 2 Conversion cycle tCAL Calibration time fADC = 35 MHz 2.35 µs -82 1/fADC tLATR Trigger conversion latency for regular and injected channels without aborting the conversion CKMODE = 00 2 - 3 1/fADC CKMODE = 01 6.5 1/fPCLK CKMODE = 10 12.5 CKMODE = 11 3.5 ts Sampling time fADC = 35 MHz 0.043 - 4.59 µs 1.5 - 160.5 1/fADC tADCVREG_S TUP ADC voltage regulator start-up time -- - 20 µs tCONV Total conversion time (including sampling time) fADC = 35 MHz Resolution = 12 bits 0.40 - 4.95 µs Resolution = 12 bits ts + 12.5 cycles for successive approximation = 14 to 173 1/fADC tIDLE Laps of time allowed between two conversions without rearm -- - 100 µs IDDA(ADC) ADC consumption from VDDA fs = 2.5 MSps - 410 - µA fs = 1 MSps - 164 - fs = 10 kSps - 17 - IDDV(ADC) ADC consumption from VREF+ fs = 2.5 MSps - 65 - µA fs = 1 MSps - 26 - fs = 10 kSps - 0.26 - 1. Specified by design – Not tested in production. 2. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate functions for further details. Table 53. ADC characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit |
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