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STM32C011F6U6 Datasheet(PDF) 12 Page - STMicroelectronics |
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STM32C011F6U6 Datasheet(HTML) 12 Page - STMicroelectronics |
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12 / 94 page  Functional overview STM32C011x4/x6 12/94 DS13866 Rev 3 Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: memory readout protection: the flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected – Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in RAM and bootloader selection are disabled. This selection is irreversible. • Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity. 3.4 Embedded SRAM STM32C011x4/x6 devices have 6 Kbytes of embedded SRAM with parity. Hardware parity check allows memory data errors to be detected, which contributes to increasing functional safety of applications. The memory can be read/write-accessed at CPU clock speed, with 0 wait states. 3.5 Boot modes At startup, the boot pin and boot selector option bit are used to select one of the three boot options: • boot from User flash memory • boot from System memory • boot from embedded SRAM The boot pin is shared with a standard GPIO and can be enabled through the boot selector option bit. The boot loader is located in System memory. It manages the flash memory reprogramming through one of the following interfaces: • USART on pins PA9/PA10 • I2C-bus on pins PB6/PB7 Table 3. Access status versus readout protection level and execution modes Area Protection level User execution Debug, boot from RAM or boot from system memory (loader) Read Write Erase Read Write Erase User memory 1 Yes Yes Yes No No No 2 Yes Yes Yes N/A N/A N/A System memory 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A Option bytes 1 Yes Yes Yes Yes Yes Yes 2 Yes No No N/A N/A N/A |
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