DA9066 datasheet(6/257 Pages) RENESAS

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DA9066

System PMIC for Dual/Quad-Core Processors

Datasheet

Revision 2.1

21-Feb-2022

CFR0011-120-00

6 of 256

12.3.1

Variable High-Pass Audio Filter (DC Cut) ......................................................... 114

12.3.2

Variable High-Pass Filter (Wind Noise Filtering) ............................................... 115

12.3.3

ADC and DAC 5-Band Equalizers ..................................................................... 115

12.3.4

Automatic Level Control (ALC) .......................................................................... 121

12.3.5

Soft Mute ........................................................................................................... 123

12.3.6

Playback Noise Gate ......................................................................................... 123

12.4 Clock Generation .............................................................................................................. 124

12.4.1

MCLK Input........................................................................................................ 124

12.4.2

Audio Reference Oscillator................................................................................ 124

12.4.3

Phase Locked Loop (PLL) ................................................................................. 124

12.4.4

Clock Modes ...................................................................................................... 124

12.4.4.1

Bypass PLL Mode (AIF Master) .................................................... 125

12.4.4.2

Normal PLL Mode (AIF Master)..................................................... 126

12.4.4.3

SRM Mode (AIF Slave).................................................................. 127

12.4.4.4

Operating with a 2 MHz to 5 MHz MCLK ...................................... 127

12.4.5

Music Mode ....................................................................................................... 128

12.4.6

ADC Voice Mode ............................................................................................... 128

12.4.7

DAC Voice Mode ............................................................................................... 128

12.4.8

Cut-Off Frequency in Voice Mode ..................................................................... 128

12.4.9

Digital Routing ................................................................................................... 129

12.5 Digital Interfaces ............................................................................................................... 130

12.5.1

I2C Control Interface (CIF) ................................................................................. 130

12.5.1.1

I2C Control Interface Protocol ........................................................ 131

12.5.2

Digital Audio Interface........................................................................................ 133

12.5.2.1

I2S Mode ........................................................................................ 133

12.5.2.2

Left Justified Mode......................................................................... 134

12.5.2.3

Right Justified Mode ...................................................................... 134

12.5.2.4

DSP Mode ..................................................................................... 134

12.5.2.5

TDM Mode ..................................................................................... 135

12.5.2.6

AIF Clocking .................................................................................. 135

12.6 Power Supplies ................................................................................................................. 136

12.7 Reference Generation....................................................................................................... 136

12.7.1

Audio References .............................................................................................. 136

13 Audio Register Map................................................................................................................... 137

14 Package Information ................................................................................................................. 143

14.1 Package Outline................................................................................................................ 143

15 Ordering Information ................................................................................................................ 144

Appendix A PMIC Register Descriptions ...................................................................................... 145

A.1

Status / Config................................................................................................................... 145

A.2

GPIO ................................................................................................................................. 155

A.3

Sequencer......................................................................................................................... 157

A.4

Supplies ............................................................................................................................ 164

A.5

Mode Control..................................................................................................................... 184

A.6

Control............................................................................................................................... 200

A.7

ADC................................................................................................................................... 206

A.8

RTC ................................................................................................................................... 213

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