DA9066 datasheet(8/257 Pages) RENESAS

8 / 257 page

DA9066

System PMIC for Dual/Quad-Core Processors

Datasheet

Revision 2.1

21-Feb-2022

CFR0011-120-00

8 of 256

Figures

Figure 1: Block Diagram ........................................................................................................................ 2

Figure 2: Connection Diagram ............................................................................................................ 14

Figure 3: Single-Phase Buck Block Diagram ...................................................................................... 55

Figure 4: Dual-Phase Buck Block Diagram ......................................................................................... 55

Figure 5: RF Buck Block Diagram ....................................................................................................... 56

Figure 6: SmartMirror LDO .................................................................................................................. 58

Figure 7: GPADC Block Diagram ........................................................................................................ 59

Figure 8: Track and Hold Sequence Timing Diagram ......................................................................... 60

Figure 9: Sequence of Automatic ADC Measurements ...................................................................... 60

Figure 10: System Voltage Monitoring ................................................................................................ 62

Figure 11: 32 kHz Crystal Oscillator.................................................................................................... 64

Figure 12: Operating Modes................................................................................................................ 67

Figure 13: nONKEY ON ...................................................................................................................... 71

Figure 14: nJIG_ON ON ...................................................................................................................... 71

Figure 15: TA ON ................................................................................................................................ 72

Figure 16: Wakeup from SLEEP ......................................................................................................... 72

Figure 17: Wakeup from RTC.............................................................................................................. 73

Figure 18: Control from MCTL pins ..................................................................................................... 74

Figure 19: GPIO Block Diagram .......................................................................................................... 77

Figure 20: Typical Startup Diagram..................................................................................................... 78

Figure 21: Example Startup of DA9066 Powering Up System Supplies ............................................. 80

Figure 22: I2C Interface ....................................................................................................................... 81

Figure 24: DA9066 Audio with Shared PMIC Connections................................................................. 87

Figure 25: I2C Control Bus Timing Diagram ........................................................................................ 98

Figure 26: Digital Audio Interface Timing Diagram ........................................................................... 100

Figure 27: Audio Input Routing Signal Paths and Gain Ranges ....................................................... 101

Figure 28: Analog Microphone Configurations .................................................................................. 102

Figure 29: Digital Microphone Timing................................................................................................ 103

Figure 30: AAD Application Diagram................................................................................................. 105

Figure 31: Analog Output Routing Signal Paths ............................................................................... 106

Figure 32: Input (clk) and Output Clocks (cp_clk and cp_clk2) at CP_FCONTROL = 010............... 111

Figure 33: ADC and DAC DC Blocking (Cut-

Off Frequency Setting ‘00’ to ‘11’, 16 kHz) ................. 114

Figure 34: ADC Equalizer Filter Band 1 Frequency Response at FS = 48 kHz................................ 116

Figure 35: ADC Equalizer Filter Band 2 Frequency Response at FS = 48 kHz................................ 117

Figure 36: ADC Equalizer Filter Band 3 Frequency Response at FS = 48 kHz................................ 117

Figure 37: ADC Equalizer Filter Band 4 Frequency Response at FS = 48 kHz................................ 118

Figure 38: ADC Equalizer Filter Band 5 Frequency Response at FS = 48 kHz................................ 118

Figure 39: DAC Equalizer Filter Band 1 Frequency Response at FS = 48 kHz................................ 119

Figure 40: DAC Equalizer Filter Band 2 Frequency Reponse at FS = 48 kHz ................................. 119

Figure 41: DAC Equalizer Filter Band 3 Frequency Response at FS = 48 kHz................................ 120

Figure 42: DAC Equalizer Filter Band 4 Frequency Response at FS = 48 kHz................................ 120

Figure 43: DAC Equalizer Filter Band 5 Frequency Response at FS = 48 kHz................................ 121

Figure 44: Operation of ALC.............................................................................................................. 122

Figure 45: Attack, Delay and Hold Parameters ................................................................................. 123

Figure 46: Wind Noise High-Pass Filter (Cut-

Off Frequency Setting ‘000’ to ‘111’, 16 kHz) ............ 129

Figure 47: Schematic of I2C Control Interface Bus............................................................................ 130

Figure 48: Timing of I2C START and STOP conditions..................................................................... 131

Figure 49: I2C Byte Write (DATA signal) ........................................................................................... 131

Figure 50: Examples of I2C Byte Read (DATA signal) ...................................................................... 132

Figure 51: Examples of I2C Page Read (DATA signal) ..................................................................... 132

Figure 52: I2C Repeated Write (DATA signal)................................................................................... 132

Figure 53: I2C Repeated Write (DATA signal)................................................................................... 133

Figure 54: I2S Format AIF Data ......................................................................................................... 133

Figure 55: Left Justified Format AIF Data ......................................................................................... 134

Figure 56: Right Justified Format AIF Data ....................................................................................... 134

Figure 57: DSP Format AIF Data ...................................................................................................... 134

Figure 58: TDM DSP Format............................................................................................................. 135

Figure 59: TDM Left Justified Format................................................................................................ 135

DA9066 Datasheet(PDF) 8 Page - Renesas Technology Corp

DA9066 Datasheet(HTML) 8 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL