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DA9066 Datasheet(PDF) 2 Page - Renesas Technology Corp |
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DA9066 Datasheet(HTML) 2 Page - Renesas Technology Corp |
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2 / 257 page  DA9066 System PMIC for Dual/Quad-Core Processors Datasheet Revision 2.1 21-Feb-2022 CFR0011-120-00 2 of 256 © 2022 Renesas Electronics Block Diagram POWER MANAGER ON / OFF CONTROL RESET GENERATION OTP - PROGRAMMABLE WAKE - UP AND SHUTDOWN SEQUENCING CONTROL SYSTEM MONITOR INTERRUPT HANDLER BACKUP CHARGER TEMP SENSOR VOLTAGE SUPER - VISION RTC 32kHz OSC RTC DIGITAL REF VOLTAGE BIASING CIRCUIT INTERNAL OSC DIG CTRL VBUS DIG CTRL DIG CTRL VLDO7 VLDO 8 DIG CTRL DIG CTRL VLDO5 VLDO6 DIG CTRL DIG CTRL DIG CTRL DIG CTRL DIG CTRL Linear CHARGER MUIC VDDCORE 2.2uF DIG CTRL 32kHz Crystal VBBAT ( 2 – 3.3V) OUT2_32K TA nRESET nIRQ nONKEY nVDD_ FAULT 220k VREF IREF VBAT VDDCORE OTP MEMORY WATCH DOG TIMER 470nF VREF_LN BUCK5 10uF 10uF DIG CTRL VDDCORE 2.2uF DIG CTRL LDOCORE 2.5V M_ CTL2 10uF BUCK PERI(1) 10uF Power Management RTC REG VDDRTC 1uF 1uF 1uF 1uF 1uF 1uF VDD_ LDO_ J VDD_ LDO_B VDD_ LDO_D 1uF 2.2uF 2.2uF DIG CTRL nJIG_ON VDDIO TP VPP 2.2uF 1uF VLDO_ AUD1 1uF LDO_ AUDIO1 2.5V VDD_LDO_AUD1 I2C INTERFACE SCL SDA M_ CTL1 Audio D9066 LDO5 1. 2 – 3.3V LDO6 1. 2 – 3.3V LDO9 1. 2 – 3.3V LDO8 1. 2 – 3.3V LDO7 1. 2 – 3.3V VLDO 9 1uF VLDO10 LDO10 1. 2 – 3.3V LDO11 1. 2 – 3.3V LDO12 1. 2 – 3.3V LDO13 1. 2 – 3.3V VLDO11 VLDO12 2.2uF VLDO13 2.2uF LDO14 1. 2 – 3.3V VLDO14 VLDO15 VLDO16 LDO15 1. 2 – 3.3V LDO16 1. 2 – 3.3V DIG CTRL 1uF DIG CTRL 1uF VLDO17 VLDO 18 LDO17 1. 2 – 3.3V LDO18 1. 2 – 3.3V VDD_ LDO_G 2.2uF GENERAL PURPOSE 12 BIT ADC VDDCORE DIG CTRL VBAT_S VF TEMP1 1uF TEMP2 BUCK2 BUCK3 BUCK4 4.7uF BUCK6 22uF 1uH VBAT VBUCK1 BUCK1 DVS DAC VBAT 1uH 22uF AUD2 1uF LDO_ AUDIO2 3.3V VLDO_ VDD_LDO_AUD2 DIG CTRL 1uF 1uF VDD_ LDO_A VDD_ LDO_F DIG CTRL 1uF DIG CTRL 1uF VLDO19 VLDO 20 LDO19 1. 2 – 3.3V LDO20 1. 2 – 3.3V VDD_ LDO_C OUT1_32K VREF_1V0 2.2uF AUX_L MICBIAS2 MIC2_P HP_R SPKR_P SPKR_N CHGPUMP DAC PLL & SRM ADC ADC DAC REFS & BIAS AIF MIC3_N DMICIN MIC3_P DMICCLK DIGITAL LDO HP_L MICBIAS1 RCVR_P RCVR_N VDD_SPKR SPKR_GND AUX_R GND_A MIC1_P MIC1_N ACC DET HP_ SENSE MICDET MICBIAS3 MIC2_N AVBAT THD PWR LIMIT CIF ADCIN JACKDET 200mA 200mA 200mA 200mA 200mA 150mA 150mA 300mA 300mA 300mA 400mA 150mA 150mA 150mA 150mA 150mA 0.8A 0.6A 0.6A 1.0A 1.2A 3.0A VDD_CP GND_SPKR Figure 1: Block Diagram |
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