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DA9066 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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DA9066 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 257 page  DA9066 System PMIC for Dual/Quad-Core Processors Datasheet Revision 2.1 21-Feb-2022 CFR0011-120-00 1 of 256 © 2022 Renesas Electronics General Description DA9066 combines an ultra-low-power audio codec with core power management functions targeting standalone application processors and mobile phones. All linear regulators use Dialog’s SmartMirror ™ dynamic biasing technique, which maintains high performance over a wide range of operating conditions and a power saving mode (Sleep mode) to minimize the quiescent current. The regulators have output voltages independently programmable via the device control interface. The buck converters do not require external Schottky diodes and offer a Sleep mode (PFM mode) for optimal efficiency at low-load currents. All DC-DC converters use a 2 MHz or 3 MHz switching frequency giving high efficiency and allowing the use of small external inductors (down to 1 µH). Beside the power modules there are different core modules like real time clock (RTC), general purpose 12-bit ADC (GPADC) and general purpose IO pins (GPIO) implemented on the IC. These support different functions such as battery voltage supervision and device over-temperature protection. DA9066 can be completely controlled from the host software writes to registers, which brings high flexibility to the design of applications. DA9066 contains an audio codec, which supports simultaneously stereo line input with up to three microphones with dual switchable bias. Comprehensive analog mixing and bypass paths to the output drivers are available. By optimizing both the power and signal chain paths for performance and efficiency it can provide 98 dB SNR at the headphone while consuming less than 5 mW from the battery. The headphone output is true-ground with integrated charge pump. A dedicated mono line out channel is provided for speaker or beep functionality. Digital audio transfer to and from the external processor is via bidirectional I2S interface which supports all common sample rates. The device may be operated in slave or master modes using the internal phase-locked loop (PLL), which may be powered down. To fully optimize each customer application, a range of built-in filtering, equalization, or audio DSP enhancements are available. These are accessible by the processor over the 2-wire serial interface and can be used to minimize latency and power consumption. Key Features ■ Operating range 2.5 V to 5.0 V ■ Twenty programmable LDO regulators ■ One dual-phase 3 A buck converter ■ Four single-phase buck converters ■ One high-efficiency RF buck converter ■ Low-power backup battery charger ■ 32 kHz real-time clock (RTC) with alarm capability ■ 12-bit general purpose ADC with auto-mode controller ■ Accurate bandgap reference ■ Temperature/voltage supervision ■ High-speed I2C interface ■ OTP memory ■ Full low-power audio codec ■ 98 dB stereo output into 16 Ω to 32 Ω headphones ■ Minimum external components; capless, true- ground driver eliminates bulky headphone coupling capacitors ■ Supports three microphones with separate low-noise microphone bias outputs ■ Low-power PLL provides system clocking and audio sample rate flexibility ■ Built-in 5-band EQ, ALC, and noise gate DSP functions ■ WLCSP, 5.8 mm x 4.8 mm, 0.4 mm pitch Applications ■ Smartphones and mobile phones ■ Ultrabooks, tablet PCs, and eBook readers ■ Portable navigation devices, ■ TV and media players |
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