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HC05RC17GRS/D Datasheet(PDF) 53 Page - NXP Semiconductors |
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HC05RC17GRS/D Datasheet(HTML) 53 Page - NXP Semiconductors |
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53 / 128 page  Resets Internal Resets MC68HC05RC17 — Rev. 2.0 General Release Specification Resets 5.5.2.5 COP Register The COP register is shared with the LSB of an unimplemented user interrupt vector as shown in Figure 5-3. Reading this location returns whatever user data has been programmed at this location. Writing a 0 to the COPR bit in this location clears the COP watchdog timer. 5.5.3 Illegal Address An illegal address reset is generated when the CPU attempts to fetch an instruction from I/O address space ($0000 to $001F). Address: $3FF0 Bit 7 654321 Bit 0 Read: X X X X X X X X Write: COPR Reset: ——————— 0 = Unimplemented Figure 5-3. COP Watchdog Timer Location Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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