TL16C752B-EP

3.3-V DUAL UART WITH 64-BYTE FIFO

SGLS153 – FEBRUARY 2003

10

POST OFFICE BOX 655303

functional description (continued)

Table 4. Interrupt Control Functions

IIR[5–0]

PRIORITY

LEVEL

INTERRUPT

TYPE

INTERRUPT SOURCE

INTERRUPT RESET METHOD

000001

None

None

None

None

000110

1

Receiver line

status

OE, FE, PE, or BI errors occur in characters in

the RX FIFO

FE, PE, BI: All erroneous characters are read

from the RX FIFO.

OE: Read LSR

001100

2

RX timeout

Stale data in RX FIFO

Read RHR

000100

2

RHR interrupt

DRDY (data ready)

(FIFO disable)

RX FIFO above trigger level (FIFO enable)

Read RHR

000010

3

THR interrupt

TFE (THR empty)

(FIFO disable)

TX FIFO passes above trigger level (FIFO

enable)

Read IIR OR a write to the THR

000000

4

Modem status

MSR[3:0] = 0

Read MSR

010000

5

Xoff interrupt

Receive Xoff character(s)/special character

Receive Xon character(s)/Read of IIR

100000

6

CTS, RTS

RTS pin or CTS pin change state from active

(low) to inactive (high)

Read IIR

It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt.

LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors

remaining in the FIFO. LSR[4 – 2] always represent the error status for the received character at the top of the

RX FIFO. Reading the RX FIFO updates LSR[4 – 2] to the appropriate status for the new character at the top

of the FIFO. If the RX FIFO is empty, then LSR[4 – 2] are all zeros.

For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon

flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read

of the LSR.

interrupt mode operation

In interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the receiver and transmitter

by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line stats register (LSR) to see

if any interrupt needs to be serviced. Figure 5 shows interrupt mode operation.

1

1

1

1

IER

IIR

THR

RHR

IOW/IOR

INT

Processor

Figure 5. Interrupt Mode Operation