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DSP56307/D Datasheet(PDF) 83 Page - NXP Semiconductors |
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DSP56307/D Datasheet(HTML) 83 Page - NXP Semiconductors |
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83 / 156 page ![]() Specifications External Memory Interface (Port A) MOTOROLA DSP56307 Technical Data 2-47 Synchronous Timings Table 2-17 External Bus Synchronous Timings1 No. Characteristics Expression2,3 100 MHz4 Unit Min Max 198 CLKOUT high to address, and AA valid5 0.25 × T C + 4.0 Ñ 6.5 ns 199 CLKOUT high to address, and AA invalid5 0.25 × T C 2.5 Ñ ns 200 TA valid to CLKOUT high (setup time) Ñ 4.0 Ñ ns 201 CLKOUT high to TA invalid (hold time) Ñ 0.0 Ñ ns 202 CLKOUT high to data out active 0.25 × T C 2.5 Ñ ns 203 CLKOUT high to data out valid 0.25 × T C + 4.0 3.3 6.5 ns 204 CLKOUT high to data out invalid 0.25 × T C 2.5 Ñ ns 205 CLKOUT high to data out high impedance 0.25 × T C Ñ 2.5 ns 206 Data in valid to CLKOUT high (setup) Ñ 4.0 Ñ ns 207 CLKOUT high to data in invalid (hold) Ñ 0.0 Ñ ns 208 CLKOUT high to RD assertion 0.75 × T C + 4.0 8.2 11.5 ns 209 CLKOUT high to RD deassertion Ñ 0.0 4.0 ns 210 CLKOUT high to WR assertion6 ¥ 100 MHz ¥ All frequencies For WS = 1 or WS ≥ 4 0.5 × T C + 4.3 For 2 ≤ WS ≤ 3 6.3 1.3 9.3 4.3 ns ns 211 CLKOUT high to WR deassertion Ñ 0.0 3.8 ns Notes: 1. External bus synchronous timings should be used only for reference to the clock and not for relative timings. 2. WS is the number of wait states specified in the BCR. 3. The asynchronous delays specified in the expressions are valid for DSP56307. 4. For operation at greater than 80MHz, we recommend that you set the asynchronous bus enable bit (ABE) in the OMR to activate asynchronous bus arbitration. 5. T198 and T199 are valid for Address Trace mode if the ATE bit in the OMR is set. Use the status of BR (See T212) to determine whether the access referenced by A0ÐA23 is internal or external, when this mode is enabled 6. If WS > 1, WR assertion refers to the next rising edge of CLKOUT. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Not Recommended for New Design |
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