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DSP56307/D Datasheet(PDF) 97 Page - NXP Semiconductors |
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DSP56307/D Datasheet(HTML) 97 Page - NXP Semiconductors |
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97 / 156 page  Specifications SCI Timing MOTOROLA DSP56307 Technical Data 2-61 SCI TIMING Table 2-20 SCI Timing No. Characteristics1 Symbol Expression 100 MHz Unit Min Max 400 Synchronous clock cycle tSCC 2 8 × T C 80.0 Ñ ns 401 Clock low period Ñ tSCC/2 − 10.0 30.0 Ñ ns 402 Clock high period Ñ tSCC/2 − 10.0 30.0 Ñ ns 403 Output data setup to clock falling edge (internal clock) ÑtSCC/4 + 0.5 × TC −17.0 8.0 Ñ ns 404 Output data hold after clock rising edge (internal clock) ÑtSCC/4 − 0.5 × TC 15.0 Ñ ns 405 Input data setup time before clock rising edge (internal clock) ÑtSCC/4 + 0.5 × TC + 25.0 50.0 Ñ ns 406 Input data not valid before clock rising edge (internal clock) ÑtSCC/4 + 0.5 × TC − 5.5 Ñ 19.5 ns 407 Clock falling edge to output data valid (external clock) Ñ Ñ Ñ 32.0 ns 408 Output data hold after clock rising edge (external clock) ÑTC + 8.0 18.0 Ñ ns 409 Input data setup time before clock rising edge (external clock) Ñ Ñ 0.0 Ñ ns 410 Input data hold time after clock rising edge (external clock) Ñ Ñ 9.0 Ñ ns 411 Asynchronous clock cycle tACC 3 64 × T C 640.0 Ñ ns 412 Clock low period Ñ tACC/2 − 10.0 310.0 Ñ ns 413 Clock high period Ñ tACC/2 − 10.0 310.0 Ñ ns 414 Output data setup to clock rising edge (internal clock) ÑtACC/2 − 30.0 290.0 Ñ ns 415 Output data hold after clock rising edge (internal clock) ÑtACC/2 − 30.0 290.0 Ñ ns Notes: 1. VCCQL = 2.5 V ± 0.25 V; TJ = −40ûC to +100 ûC, CL = 50 pF 2. tSCC = synchronous clock cycle time (For internal clock, tSCC is determined by the SCI clock control register and TC.) 3. tACC = asynchronous clock cycle time; value given for 1x Clock mode (For internal clock, tACC is determined by the SCI clock control register and TC.) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Not Recommended for New Design |
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