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DSP56307/D Datasheet(PDF) 1 Page - NXP Semiconductors |
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DSP56307/D Datasheet(HTML) 1 Page - NXP Semiconductors |
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1 / 156 page  MOTOROLA SEMICONDUCTOR TECHNICAL DATA DSP56307 Order this document by: DSP56307DS/D Rev. 0, 8/10/98 ©1998 MOTOROLA, INC. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notification. Product Preview 24-BIT DIGITAL SIGNAL PROCESSOR The Motorola DSP56307, a member of the DSP56300 family of programmable digital signal processors (DSPs), supports wireless infrastructure applications with general filtering operations. The on-chip enhanced filter coprocessor (EFCOP) processes filter algorithms in parallel with core operation, thus increasing overall DSP performance and efficiency. Like the other family members, the DSP56307 uses a high-performance, single-clock-cycle-per-instruction engine (code-compatible with Motorola's popular DSP56000 core family), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access controller, as in Figure 1. The DSP56307 offers performance at 100 million instructions (MIPS) per second using an internal 100 MHz clock with a 2.5 volt core and independent 3.3 volt input/output power. Figure 1 DSP56307 Block Diagram PLL OnCE™ Clock Generator Internal Data Bus Switch YAB XAB PAB YDB XDB PDB GDB MODB/ IRQB MODC/ IRQC External Data Bus Switch 13 MODD/ IRQD DSP56300 6 16 24-Bit 24 18 DDB DAB Peripheral Core Expansion Area 6 JTAG 5 3 RESET MODA/ IRQA PINIT/ NMI 2 EXTAL XTAL Address Control Data Address Generation Unit Six Channel DMA Unit Program Interrupt Controller Program Decode Controller Program Address Generator Data ALU 24 × 24+56→56-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter Power Mngmnt. External Bus Interface and I - Cache Control AA1367 Memory Expansion Area DE Program RAM 16 K × 24 or X Data RAM 24 K × 24 Y Data RAM 24 K × 24 External Address Bus Switch SCI Interface Enhanced Filtering Co- EFCOP processor ESSI Interface Host Interface HI08 Triple Timer (Program RAM 15 K × 24 and Instruction Cache 1024 × 24) Bootstrap ROM Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Not Recommended for New Design |
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