PIC18F6410ESLASHPTSQTP datasheet(114/404 Pages) MICROCHIP

114 / 404 page

PIC18F6310/6410/8310/8410

DS39635A-page 112

Preliminary

 2004 Microchip Technology Inc.

9.4

IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three Peripheral

Interrupt Priority registers (IPR1, IPR2, IPR3). Using

the priority bits requires that the Interrupt Priority

Enable (IPEN) bit be set.

IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

R/W-1

PSPIP

ADIP

RC1IP

TX1IP

SSPIP

CCP1IP

TMR2IP

TMR1IP

bit 7

bit 0

bit 7

PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit

=High priority

= Low priority

bit 6

ADIP: A/D Converter Interrupt Priority bit

=High priority

= Low priority

bit 5

RC1IP: EUSART Receive Interrupt Priority bit

=High priority

= Low priority

bit 4

TX1IP: EUSART Transmit Interrupt Priority bit

=High priority

= Low priority

bit 3

SSPIP: Master Synchronous Serial Port Interrupt Priority bit

=High priority

= Low priority

bit 2

CCP1IP: CCP1 Interrupt Priority bit

=High priority

= Low priority

bit 1

TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

=High priority

= Low priority

bit 0

TMR1IP: TMR1 Overflow Interrupt Priority bit

=High priority

= Low priority

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

PIC18F6410E/PTSQTP Datasheet(PDF) 114 Page - Microchip Technology

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