S75WS256NDFBAWMB datasheet(31/216 Pages) SPANSION

31 / 216 page

February 17, 2005 S75WS-N-00_A0

S75WS256Nxx Based MCPs

Advance

Information

Reading the Configuration Table. The configuration register can be read with a four-cycle com-

mand sequence. See Table 13.1 for sequence details. Once the data has been read from the

configuration register, a software reset command is required to set the device into the correct

state.

8.4

Autoselect

The Autoselect is used for manufacturer ID, Device identification, and sector protection informa-

tion. This mode is primarily intended for programming equipment to automatically match a device

with its corresponding programming algorithm. The Autoselect codes can also be accessed in-sys-

tem. When verifying sector protection, the sector address must appear on the appropriate highest

order address bits (see Table 8.9). The remaining address bits are don't care. The most significant

four bits of the address during the third write cycle selects the bank from which the Autoselect

codes are read by the host. All other banks can be accessed normally for data read without exiting

the Autoselect mode.

To access the Autoselect codes, the host system must issue the Autoselect command.

Table 8.8 Configuration Register

CR Bit

Function

Settings (Binary)

CR15

Set Device Read

Mode

0 = Synchronous Read (Burst Mode) Enabled

1 = Asynchronous Read Mode (default) Enabled

CR14

Boundary Crossing

54 MHz 66 Mhz 80 MHz

S29WS064N

S29WS128N

N/A

Default value is 0

S29WS256N

0 = No extra boundary crossing latency

1 = With extra boundary crossing latency (default)

Must be set to 1 greater than 54 MHz.

CR13

Programmable

Wait State

S29WS064N

S29WS128N

011 = Data valid on 5th active CLK

edge after addresses latched

100 = Data valid on 6th active CLK

edge after addresses latched

101 = Data valid on 7th active CLK

edge after addresses latched (default)

110 = Reserved

111 = Reserved

Inserts wait states before initial data

is available. Setting greater number of wait

states before initial data reduces latency

after initial data. (Notes 1, 2)

S29WS256N

CR12

S29WS064N

S29WS128N

S29WS256N

CR11

S29WS064N

S29WS128N

S29WS256N

CR10

RDY Polarity

0 = RDY signal active low

1 = RDY signal active high (default)

CR9

Reserved

1 = default

CR8

RDY

0 = RDY active one clock cycle before data

1 = RDY active with data (default)

When CR13-CR11 are set to 000,

RDY is active with data regardless of CR8 setting.

CR7

Reserved

1 = default

CR6

Reserved

1 = default

CR5

Reserved

0 = default

CR4

Reserved

0 = default

CR3

Burst Wrap Around

0 = No Wrap Around Burst

1 = Wrap Around Burst (default)

CR2

CR1

CR0

Burst Length

000 = Continuous (default)

010 = 8-Word Linear Burst

011 = 16-Word Linear Burst

100 = 32-Word Linear Burst

(All other bit settings are reserved)

Notes:

1. Refer to Tables 8.2 - 8.6 for wait states requirements.

2. Refer to Synchronous Burst Read timing diagrams

3. Configuration Register is in the default state upon power-up or hardware reset.

S75WS256NDFBAWMB Datasheet(PDF) 31 Page - SPANSION

S75WS256NDFBAWMB Datasheet(HTML) 31 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL