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S75WS256NDFBAWMB Datasheet(PDF) 78 Page - SPANSION |
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S75WS256NDFBAWMB Datasheet(HTML) 78 Page - SPANSION |
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78 / 216 page  76 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005 Ad van c e Inf o rmation Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. In progress and complete refer to status of program operation. 3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during command sequence unlock cycles. 4. CLK can be either VIL or VIH. 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register. Figure 12.14 Asynchronous Program Operation Timings OE# CE# Data Addresses AVD WE# CLK VCC 555h PD tAS tAVSW tAVHW tAH tWC tWPH PA tVCS tWP tDH tCH In Progress tWHWH1 VA Complete VA Program Command Sequence (last two cycles) Read Status Data tDS VIH VIL tAVDP A0h tCS tCAS |
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