UPD75P218KB datasheet(7/38 Pages) RENESAS

7 / 38 page

µPD75P218

1.2

NON-PORT PINS

Pin name

T0 - T9

T10/S15 -

T13/S12

T14/S11,

T15/S10

S0 - S8

PPO

TI0

SCK

INT4

INT0

INT1

INT2

BUZ

X1, X2

XT1, XT2

RESET

MD0 - MD3

VPP

VLOAD

VDD

VSS

NC Note 3

Function

Note 1

High breakdown voltage large current output pin

for digit output

Note 2

High breakdown voltage large current output pin

for digit/segment output

The remainder of the pins can be used as PORTH.

High breakdown voltage large current output pin

for digit/segment output

Static output is also available.

High breakdown voltage output pin for segment

output

Static output is also available.

Note 1

High breakdown voltage output pin for segment

output

Output for receiving pulse signal for timer/pulse generator

Input for receiving external event pulse signal for timer/

event counter

Serial clock I/O

Serial data output or serial data I/O

Serial data input or normal input

Edge detection vectored interrupt input

(either rising edge or falling edge detection)

Edge detection vectored interrupt input with noise elimination

(detection edge selectable)

Edge detection testable input (rising edge detection)

Fixed frequency output pin (for buzzer or system clock trimming)

Crystal/ceramic resonator connection for main system clock

generation.

When external clock is used, it is applied to X1, and its

reserve phase signal is applied to X2.

Crystal connection for subsystem clock generation.

When external clock is used, it is applied to XT1, and XT2 is open.

System reset input (low level active)

Operation mode selection pins during the PROM write/verify cycles

+12.5 V is applied as the programming voltage during the

PROM write/verify cycles

Pull-down resistor connection pin of FIP® controller/driver

Positive power supply. +6 V is applied as the programming

voltage during the PROM write/verify cycles

GND potential

No connection

When reset

Low level

High

impedance

Low level

High

impedance

Input

Input/

output

Output

Input

I/O

Input

I/O

Input

I/O

Shared

–

PH3 - PH0

–

P13

P01

P02

P03

P00

P10/VPP

P11

P12

P23

–

P30 - P33

P10/INT0

–

Note 1. On-chip pull-down resistor

2. Open drain output

3. When using a printed board with a

µPD75216A, 75217, or 75218, connect the NC pin to the VPRE.

UPD75P218KB Datasheet(PDF) 7 Page - Renesas Technology Corp

UPD75P218KB Datasheet(HTML) 7 Page - Renesas Technology Corp

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