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UPD75P218KB Datasheet(PDF) 27 Page - Renesas Technology Corp |
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UPD75P218KB Datasheet(HTML) 27 Page - Renesas Technology Corp |
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27 / 38 page  25 µPD75P218 Cautions 1. VPP must not exceed +13.5 V, including overshoot. 2. VDD is to be applied prior to VPP and to be removed after VPP is removed. AC Programming Characteristics (Ta = 25 ± 5 ˚C, V DD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V) DC Programming Characteristics (Ta = 25 ± 5 ˚C, V DD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V) Parameter High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage VDD power supply current VPP power supply current Conditions All except X1, X2 X1, X2 All except X1, X2 X1, X2 VIN = VIL or VIH IOH = –1 mA IOL = 1.6 mA MD0 = VIL, MD1 = VIH MIN. 0.7VDD VDD – 0.5 0 0 VDD – 1.0 Unit V V V V µA V V mA mA MAX. VDD VDD 0.3VDD 0.4 10 0.4 30 30 TYP. Symbol VIH1 VIH2 VIL1 VIL2 ILI VOH VOL IDD IPP Parameter Address setup time Note 2 (to MD0 ↓) MD1 setup time (to MD0 ↓) Data setup time (to MD0 ↓) Address hold time Note 2 (from MD0 ↑) Data hold time (from MD0 ↑) MD0 ↑ → data output float delay time VPP setup time (to MD3 ↑) VDD setup time (to MD3 ↑) Initialized program pulse width Additional program pulse width MD0 setup time (to MD1 ↑) MD0 ↓ → data output delay time MD1 hold time (to MD0 ↑) MD1 recovery time (from MD0 ↓) Program counter reset time X1 input low- and high-level width X1 input frequency Initial mode set time MD3 setup time (to MD1 ↑) MD3 hold time (from MD1 ↓) MD3 setup time (to MD0 ↓) Address Note 2 → Data output delay time Address Note 2 → Data output hold time MD3 hold time (from MD0 ↑) MD3 ↓ → Data output float delay time TYP. 1.0 MAX. 130 1.05 21.0 1 4.19 130 Unit µs µs µs µs µs ns µs µs ms ms µs µs µs µs µs µs MHz µs µs µs µs µs ns µs µs MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2 2 2 10 0.125 2 2 2 2 2 0 2 2 Conditions MD0 = MD1 = VIL tM1H + tM1R ≥ 50 µs During program read cycle During program read cycle During program read cycle During program read cycle During program read cycle Note 1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR – – – – – – – tACC tOH – – Symbol tAS TM1S tDS TAH tDH tDF tVPS tVDS tPW tOPW tM0S tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR Notes 1. These symbols correspond to those of the µPD27C256A. 2. The internal address signal is incremented by the rising edge of the fourth X1 pulse; it is not connected to an external pin. |
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