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UPD75P218KB Datasheet(PDF) 23 Page - Renesas Technology Corp

Part # UPD75P218KB
Description  MOS INTEGRATED CIRCUIT
PDF  38 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD75P218KB Datasheet(HTML) 23 Page - Renesas Technology Corp

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21
µPD75P218
Notes 1. The CPU clock (
Φ) cycle time is deter-
mined by the oscillator frequency of the
connected resonator, the system clock
control register (SCC), and the processor
clock control register (PCC).
The right chart shows the cycle time tCY
characteristics for power supply voltage
VDD during the main system clock opera-
tion.
2. 2tCY or 128/fXX, depending on the setting
of the interrupt mode register (IM0).
Guaranteed
operating
range
02
3
4
5
6
1
(Main system clock)
0.5
1
2
3
4
5
6
30
32
40
tCY
VDD
vs
Power supply voltage VDD (V)



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