Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

UPD703003A Datasheet(PDF) 21 Page - Renesas Technology Corp

Part # UPD703003A
Description  MOS INTEGRATED CIRCUIT
PDF  45 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD703003A Datasheet(HTML) 21 Page - Renesas Technology Corp

Back Button UPD703003A Datasheet HTML 17Page - Renesas Technology Corp UPD703003A Datasheet HTML 18Page - Renesas Technology Corp UPD703003A Datasheet HTML 19Page - Renesas Technology Corp UPD703003A Datasheet HTML 20Page - Renesas Technology Corp UPD703003A Datasheet HTML 21Page - Renesas Technology Corp UPD703003A Datasheet HTML 22Page - Renesas Technology Corp UPD703003A Datasheet HTML 23Page - Renesas Technology Corp UPD703003A Datasheet HTML 24Page - Renesas Technology Corp UPD703003A Datasheet HTML 25Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 45 page
background image
19
µPD703003A, 703004A, 703025A, 703003A(A), 703025A(A)
Data Sheet U13188EJ6V1DS
Data Retention Characteristics (TA = –40 to +85
°C, VDD = VDDDR)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data retention voltage
VDDDR
STOP mode
1.5
5.5
V
Data retention current
IDDDR
Note 1
0.4VDDDR
50
µA
Note 2
0.4VDDDR
200
µA
Power supply voltage rise time
tRVD
200
µs
Power supply voltage fall time
tFVD
200
µs
Power supply voltage hold time
tHVD
0ms
(vs. STOP mode setting)
STOP mode release signal input time tDREL
Note 3
0ns
Data retention high-level input voltage
VIHDR
Note 3
0.9VDDDR
VDDDR
V
Data retention low-level input voltage
VILDR
0
0.1VDDDR
V
Notes 1. –40
°C ≤ TA ≤ +50°C
2. 50
°C <TA ≤ 85°C
3. P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, X1, and
their alternate-function pins.
Remark
TYP. values are reference values for when TA = 25
°C (except for the conditions in Note 2) and VDD =
5.0 V.
tHVD
VDD
VDD
tFVD
tRVD
tDREL
VDD
VDDDR
RESET (input)
VIHDR
NMI (input)
(Released at falling edge)
VIHDR
VILDR
NMI (input)
(Released at rising edge)
STOP mode setting (fifth clock after PSC register is set)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com