WM8753LGEFLSLASHV datasheet(55/92 Pages) WOLFSON

55 / 92 page

WM8753L

Pre-Production

PP Rev 3.4 November 2005

LEFT CHANNEL

RIGHT CHANNEL

LRC /

VXFS

BCLK /

VXCLK

DACDAT /

ADCDAT /

VXDIN /

VXDOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 19 Right Justified Audio Interface (assuming n-bit word length)

In I

2S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The

other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency

and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of

the next.

LEFT CHANNEL

RIGHT CHANNEL

LRC /

VXFS

BCLK /

VXCLK

DACDAT /

ADCDAT /

VXDIN /

VXDOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

Figure 20 I

2S Justified Audio Interface (assuming n-bit word length)

DSP MODE

In DSP/PCM mode, the left channel MSB is available on either the 1

st (mode B) or 2nd (mode A) rising

edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately

follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be

unused BCLK cycles between the LSB of the right channel data and the next sample.

In device master mode, the LRC output will resemble the frame pulse shown in Figure 21 and Figure

22. In device slave mode, Figure 23 and Figure 24, it is possible to use any length of frame pulse less

than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before

the rising edge of the next frame pulse.

Figure 21 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)

WM8753LGEFL/V Datasheet(PDF) 55 Page - Wolfson Microelectronics plc

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