T89C51RC2-3CSIM datasheet(20/117 Pages) ATMEL

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T89C51RB2/RC2

4105D–8051–10/06

Registers

Table 10. AUXR Register

AUXR - Auxiliary Register (8Eh)

Reset Value = XX0X 00’HSB. XRAM’0b (See Table 70)

Not bit addressable

XRS1

XRS0

EXTRAM

Bit

Number

Bit

Mnemonic

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

5M0

Pulse length

Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock

periods (default).

Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock

periods.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3XRS1

XRAM Size

XRS1

XRS0

XRAM size

256 bytes (default)

512 bytes

768 bytes

1024 bytes

2XRS0

EXTRAM

EXTRAM bit

Cleared to access internal XRAM using movx @ Ri/ @ DPTR.

Set to access external memory.

Programmed by hardware after Power-up regarding Hardware Security Byte

(HSB), default setting, XRAM selected.

0AO

ALE Output bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if

X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC

instruction is used.

T89C51RC2-3CSIM Datasheet(PDF) 20 Page - ATMEL Corporation

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