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AT89C51AC3-RDTIM Datasheet(PDF) 116 Page - ATMEL Corporation |
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AT89C51AC3-RDTIM Datasheet(HTML) 116 Page - ATMEL Corporation |
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116 / 143 page  116 AT89C51AC3 4383B–8051–01/05 Table 66. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register Reset Value = xxxx 0x0xb bit addressable 76 543 210 - - - - ESPI - EADC - Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3 ESPI SPI Interrupt Enable bit Clear to disable the SPI interrupt. Set to enable the SPI interrupt. 2- Reserved The value read from this bit is indeterminate. Do not set this bit. 1 EADC ADC Interrupt Enable bit Clear to disable the ADC interrupt. Set to enable the ADC interrupt. 0- Reserved The value read from this bit is indeterminate. Do not set this bit. |
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