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AT89C51AC3-RDTIM Datasheet(PDF) 118 Page - ATMEL Corporation |
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AT89C51AC3-RDTIM Datasheet(HTML) 118 Page - ATMEL Corporation |
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118 / 143 page  118 AT89C51AC3 4383B–8051–01/05 Table 68. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register 1 Reset Value = XXXX 0X0Xb bit addressable 76 543 210 -- -- SPIL - PADCL - Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3 SPIL SPI Interrupt Priority Level Less Significant Bit Refer to SPIH for priority level. 2- Reserved The value read from this bit is indeterminate. Do not set this bit. 1PADCL ADC Interrupt Priority Level Less Significant Bit Refer to PSPIH for priority level. 0- Reserved The value read from this bit is indeterminate. Do not set this bit. |
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