PCM3060PWR datasheet(16/45 Pages) BURR-BROWN

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POWER-ON RESET AND EXTERNAL RESET SEQUENCE

PCM3060

SLAS533 – MARCH 2007

The PCM3060 has both an internal power-on reset circuit and an external reset circuit. The sequences for both

resets are shown in the following.

Figure 22 illustrates the timing of the internal power-on reset. Initialization (reset) is done automatically at the

time when VDD exceeds 2.2 V typical.

Internal reset is released 1024 SCKIx (x = 1, 2) after power on if the H/W control mode is selected and RST is

kept HIGH; then the PCM3060 begins normal operation. If the S/W control mode is selected and RST is kept

HIGH, internal reset is released 1024 SCKIx after the reset of ADPSV and DAPSV through serial control port;

then the PCM3060 begins normal operation. If RST is kept LOW, internal reset is held and the reset sequence is

frozen until RST is changed from LOW to HIGH. VOUTL and VOUTR from the DAC are forced to the VCOM (= 0.5

VCC) level as VCC rises. If synchronization is maintained among SCKIx, BCKx, and LRCKx, VOUTL and VOUTR go

into the fade-in sequence after tDACDLY1 = 2048/fS from internal reset release. Then VOUTL and VOUTR provide

outputs corresponding to DIN after tDACDLY2 = 1616/fS from the start of fade-in. Similarly, DOUT from the ADC is

enabled and goes into the fade-in sequence after tADCDLY1 = 2048/fS from internal reset release, and then DOUT

provides an output corresponding to VINL and VINR after tADCDLY2 = 1936/fS from the start of fade-in. If

synchronization is not held, the internal reset is not released and operation mode is kept on reset and

power-down state. After resynchronization, the DAC begins its fade-in sequence, and the ADC also begins

fade-in operation after internal initialization and an initial delay.

Figure 23 is the timing chart of the external reset. The RST pin initiates external forced reset when RST is held

LOW for at least tRST = 2048/fS; it resets the device places it in the power-down state, which is the lowest-power

dissipation state in the PCM3060.

When RST transitions from HIGH to LOW while SCKIx, BCKx, and LRCKx are synchronized, VOUTL and VOUTR

are forced to the VCOM (= 0.5VCC) level after the fade-out sequence lasting tDACDLY2 = 1616/fS, and DOUT is

forced to ZERO after tADCDLY2 = 1936/fS fade-out sequence. After that, the internal reset becomes LOW, the

PCM3060 resets and enters into the power-down state, finally all registers and memory except mode control

registers are reset. To resume into normal operation, changing RST to HIGH again is required, and the

sequence shown in Figure 22 is performed. It is possible to halt SCKIx, BCKx and LRCKx during the

power-down state, but all clocks must be resumed prior to starting the power-up sequence. The same

fade-in/-out sequence of VOUTL/R and DOUT can be obtained by setting the ADPSV and DAPSV bits through

serial mode control port.

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PCM3060PWR Datasheet(PDF) 16 Page - Burr-Brown (TI)