M68HC05 datasheet(68/118 Pages) FREESCALE

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Serial Communications Interface (SCI)

MC68HC05C9A Advance Information Data Sheet, Rev. 4.1

Freescale Semiconductor

TDRE — Transmit Data Register Empty Flag

This clearable, read-only flag is set when the data in the SCDR transfers to the transmit shift register.

TDRE generates an interrupt request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by reading

the SCSR with TDRE set and then writing to the SCDR. Reset sets the TDRE bit. Software must

initialize the TDRE bit to logic 0 to avoid an instant interrupt request when turning the transmitter on.

1 = SCDR data transferred to transmit shift register

0 = SCDR data not transferred to transmit shift register

TC — Transmission Complete Flag

This clearable, read-only flag is set when the TDRE bit is set, and no data, preamble, or break

character is being transmitted. TDRE generates an interrupt request if the TCIE bit in SCCR2 is also

set. Clear the TC bit by reading the SCSR with TC set, and then writing to the SCDR. Reset sets the

TC bit. Software must initialize the TC bit to logic 0 to avoid an instant interrupt request when turning

the transmitter on.

1 = No transmission in progress

0 = Transmission in progress

RDRF — Receive Data Register Full Flag

This clearable, read-only flag is set when the data in the receive shift register transfers to the SCI data

bit by reading the SCSR with RDRF set and then reading the SCDR.

1 = Received data available in SCDR

0 = Received data not available in SCDR

IDLE — Receiver Idle Flag

This clearable, read-only flag is set when 10 or 11 consecutive logic 1s appear on the receiver input.

IDLE generates an interrupt request if the ILIE bit in the SCCR2 is also set. Clear the ILIE bit by reading

the SCSR with IDLE set and then reading the SCDR.

1 = Receiver input idle

0 = Receiver input not idle

OR — Receiver Overrun Flag

This clearable, read-only flag is set if the SCDR is not read before the receive shift register receives

the next word. OR generates an interrupt request if the RIE bit in the SCCR2 is also set. The data in

the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading

the SCSR with OR set and then reading the SCDR.

1 = Receive shift register full and RDRF = 1

0 = No receiver overrun

NF — Receiver Noise Flag

This clearable, read-only flag is set when noise is detected in data received in the SCI data register.

Clear the NF bit by reading the SCSR and then reading the SCDR.

1 = Noise detected in SCDR

0 = No noise detected in SCDR

$0010

Bit 7

6543

Bit 0

Read:

TDRE

RDRF

IDLE

Write:

Reset:

11000

—

= Unimplemented

Figure 9-11. SCI Status Register (SCSR)

M68HC05 Datasheet(PDF) 68 Page - Freescale Semiconductor, Inc

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