XRT94L33IB datasheet(27/110 Pages) EXAR

27 / 110 page

XRT94L33

Rev 2

22 ...0

00 ...0

33 ---C

C H

H A

N N

N E

E L

L D

D S

S 3

33 ///E

E 3

33 ///S

S T

T S

S -

-- 1

11 T

T O

O S

S T

T S

S -

-- 3

33 ///S

S T

T M

M -

-- 1

11 M

M A

P P

P E

E R

R S

S O

O N

N E

E T

T A

T M

M ///P

P P

P –

–– H

H A

R W

W A

A R

R E

E M

M A

N U

U A

TxE1F1E2Enable

CMOS

Transmit E1-F1-E2 Byte Input Port – Enable (or Ready)

Indicator Output pin:

This output pin, along with the “TxTOHClk” output pin and the

“TxE1F1E2” input pin permit the user to insert their value for

the E1, F1 and E2 bytes, into the Transmit STS-3 TOH

Processor Block. The Transmit STS-3 TOH Processor block

will accept this data and will insert into the E1, F1 and E2 byte-

fields, within the “outbound” STS-3 data-stream.

Whatever external circuitry (which is connected to the

“TxTOHClk”, the “TxE1F1E2” and this output pin), is suppose

to do the following.

It should continuously monitor the state of this output pin.

Whenever this output pin pulses “HIGH”, then the external

circuitry should place the next “orderwire” bit (to be inserted

into the “Transmit STS-3 TOH Processor” block) onto the

“TxE1F1E2” input pin, upon the rising edge of “TxTOHClk”.

Any data that is placed on the “TxE1F1E2” input pin, will be

sampled upon the falling edge of “TxOHClk”.

TxE1F1E2Frame

CMOS

Transmit E1-F1-E2 Byte Input Port – Framing Output Pin.

This output pin pulses “HIGH” for one period of “TxTOHClk”,

one “TxTOHClk” bit-period prior to the “Transmit E1-F1-E2

Byte Input Port” expecting the very first byte of the E1 byte,

within a given “outbound” STS-3 frame.

TxE1F1E2

TTL

Transmit E1-F1-E2 Byte Input Port – Input Pin:

This input pin, along with the “TxE1F1E2Enable” and the

“TxTOHClk” output pins permit the user to insert their value for

the E1, F1 and E2 bytes, into the Transmit STS-3 TOH

Processor Block. The Transmit STS-3 TOH Processor block

will accept this data and insert it into the E1, F1 and E2 byte

fields, within the “outbound” STS-3 data-stream.

Whatever external circuitry that is interfaced to this input pin,

the “TxE1F1E2Enable” and the “TxTOHClk” pins is suppose to

do the following.

should

continuously

monitor

the

state

the

“TxE1F1E2Enable” input pin.

Whenever the “TxE1F1E2Enable” input pin pulses “HIGH”,

then the external circuitry should place the next “orderwire” bit

(to be inserted into the “Transmit STS-3 TOH Processor”

block) onto this input pin upon the rising edge of “TxTOHClk”.

Any data that is placed on the “TxE1F1E2” input pin, will be

sampled upon the falling edge of “TxTOHClk”.

Note:

This pin should be connected to GND if it is not

used.

XRT94L33IB Datasheet(PDF) 27 Page - Exar Corporation

XRT94L33IB Datasheet(HTML) 27 Page - Exar Corporation

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