Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

Preview PDF HTML

STM8L052R8T6 Datasheet(PDF) 99 Page - STMicroelectronics

Part # STM8L052R8T6
Description  Value Line, 8-bit ultralow power MCU, 64-KB Flash,256-byte data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC
PDF  109 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM8L052R8T6 Datasheet(HTML) 99 Page - STMicroelectronics

Back Button STM8L052R8T6 Datasheet HTML 95Page - STMicroelectronics STM8L052R8T6 Datasheet HTML 96Page - STMicroelectronics STM8L052R8T6 Datasheet HTML 97Page - STMicroelectronics STM8L052R8T6 Datasheet HTML 98Page - STMicroelectronics STM8L052R8T6 Datasheet HTML 99Page - STMicroelectronics STM8L052R8T6 Datasheet HTML 100Page - STMicroelectronics STM8L052R8T6 Datasheet HTML 101Page - STMicroelectronics STM8L052R8T6 Datasheet HTML 102Page - STMicroelectronics STM8L052R8T6 Datasheet HTML 103Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 99 / 109 page
background image
STM8L052R8
Electrical parameters
Doc ID023337 Rev 2
99/109
Figure 37.
ADC1 accuracy characteristics
Figure 38.
Typical connection diagram using the ADC
1.
Refer to Table 44 for the values of RAIN and CADC.
2.
Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 39 or Figure 40,
depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF
capacitors should be used. They should be placed as close as possible to the chip.
EO
EG
1LSBIDEAL
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
4095
4094
4093
5
4
3
2
1
0
7
6
1
2
3
456
7
4093 4094 4095 4096
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
ai14395b
VREF+
4096
(or
depending on package)]
VDDA
4096
[1LSBIDEAL =
ai17090e
STM8L05xxx
VDD
AINx
IL±50 nA
0.6 V
VT
RAIN(1)
Cparasitic
VAIN
0.6 V
VT
RADC
CADC(1)
12-bit
converter
Sample and hold ADC
converter



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com