PPC440SPE datasheet(7/80 Pages) AMCC

7 / 80 page

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

AMCC Proprietary

Preliminary Data Sheet

General Purpose Timers

0000 0004 F000 0A00

0000 0004 F000 0B3F

320B

Reserved

0000 0004 F000 0B40

0000 0004 FEFF FFFF

Boot ROM2, 3

EBC Bank0

0000 0004 FF00 0000

0000 0004 FFFF FFFF

16MB

Reserved

0000 0005 0000 0000

0000 0007 FFFF FFFF

Local Memory Alias (HB)

Aliased DDR SDRAM

0000 0008 0000 0000

0000 000B FFFF FFFF

16GB

PCI Space (HB)

Reserved

0000 000C 0000 0000

0000 000C 07FF FFFF

PCIX0 I/O

0000 000C 0800 0000

0000 000C 0800 FFFF

64KB

Reserved

0000 000C 0801 0000

0000 000C 0EBF FFFF

PCIX0 Addressing configuration

Regs

0000 000C 0EC0 0000

0000 000C 0EC0 0007

Reserved

0000 000C 0EC0 0008

0000 000C 0EC7 FFFF

PCIX0 Core Configuration Regs

0000 000C 0EC8 0000

0000 000C 0EC8 0FFF

4KB

Reserved

0000 000C 0EC8 1000

0000 000C 0EC8 10FF

PCIX0 Simple Message Passing

0000 000C 0EC8 1100

0000 000C 0EC8 11FF

256B

Reserved

0000 000C 0EC8 1200

0000 000C 0ECF FFFF

PCIX0 Special Cycle

0000 000C 0ED0 0000

0000 000C 0EDF FFFF

1MB

Reserved

0000 000C 0EE0 0000

0000 000C 0FFF FFFF

PCI Memory (PCI-Express & PCI-X)

0000 000C 1000 0000

0000 000C FEFF FFFF

3.8GB

PCI-X DDR boot ROM (PCI memory

0000 000C FF00 0000

0000 000C FFFF FFFF

16MB

PCI Memory (PCI-Express & PCI-X)

0000 000D 0000 0000

0000 000F FFFF FFFF

12GB

Reserved4

0000 0010 0000 0000

0FFF FFFF FFFF FFFF

Reserved5

1000 0000 0000 0000

1FFF FFFF FFFF FFFF

PCI Core Space (HB)

PCI Memory (PCI-Express & PCI-X)

2000 0000 0000 0000

FFFF FFFF FFFF FFFF

Notes:

1. DDR SDRAM and

on-chip SRAM can be located anywhere in the Local Memory area of the memory map.

2. The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While locating

volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended.

3. When the optional boot from PCI-X memory is selected, the PCI-X Boot ROM address space begins at C FF00 0000 (16 MB).

4. Never decoded.

5. Unpredictable results on Read and Write operations.

6. Accessed by means of EBC Peripheral Bank Configuration Registers.

Table 1. System Memory Address Map (Sheet 2 of 2)

Function

Sub Function

Start Address

End Address

Size

PPC440SPE Datasheet(PDF) 7 Page - Applied Micro Circuits Corporation

PPC440SPE Datasheet(HTML) 7 Page - Applied Micro Circuits Corporation

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