IIS2DULPX datasheet(19/106 Pages) STMICROELECTRONICS

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Table 10. Internal pin status

Pin #

Name

Function

Pin status

SCL

SPC

I²C/MIPI I3C® serial clock (SCL)

SPI serial port clock (SPC)

Default: input without

pull-up

SPI/I²C/MIPI I3C® mode selection

1: SPI idle mode / I²C/MIPI I3C® enabled

0: SPI enabled / I²C/MIPI I3C® disabled

Default: input with

internal pull-up

SDO

TA0

Serial data output (SDO)

I²C less significant bit of the device address (TA0)

Default: input without

internal pull-up

SDA

SDI

SDO

I²C/MIPI I3C® serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

Default: (SDA) input

without internal pull-up

Internally not connected. Can be tied to VDD, VDDIO, or GND.

GND

0 V supply

RES/EXT_CLK

Connect to GND if not used as interrupt pin 1(1) or as

External clock for the synchronization of multiple sensors(2)

GND

0 V supply

VDD

Power supply

VDDIO

Power supply for I/O pins

INT2

Interrupt pin 2. Clock input when selected in one-shot mode. AH input 2 (or Qvar electrode

2) is connected if the analog hub (or Qvar functionality) is enabled.(5)

Default: input with

internal pull-down(3)(4)

INT1

Interrupt pin 1. AH input 1 (or Qvar electrode 1) is connected if the analog hub (or Qvar

functionality) is enabled.(5)

Default: input with

internal pull-down(6)(7)

1. When the INT1_ON_RES bit of register CTRL1 (10h) is set to 1, the interrupt signals configured on the INT1 pin are routed to the

RES/EXT pin. This is useful when the analog hub / Qvar feature is enabled and the INT1 and INT2 pins are used to connect the external

analog lines or the electrodes to sense the Qvar signal.

2. When the external clock for the synchronization of multiple sensors is used, the EXT_CLK_EN bit must be set to 1 in register

EXT_CLK_CFG (08h) and the bit INT1_ON_RES set to 0 in register CTRL1 (10h) in order to correctly drive the pin.

3. The internal pull-down can be disconnected by setting the PD_DIS_INT2 bit of register PIN_CTRL (0Ch) to 1. When this is done, the INT2

pin needs to be externally biased.

4. The INT2 pin is configured as "push-pull output forced to GND" (and the internal pull-down disabled) as soon as it is configured with the

interrupt configuration bits in the CTRL3 (12h), MD2_CFG (20h), EMB_FUNC_INT2 (0Eh), FSM_INT2 (0Fh), and MLC_INT2 (11h)

registers.

5. The analog hub and Qvar functions are enabled by setting the AH_QVAR_EN bit to 1 in AH_QVAR_CFG (31h).

6. The internal pull-down can be disconnected by setting the PD_DIS_INT1 bit of register PIN_CTRL (0Ch) to 1. When this is done, the INT1

pin needs to be externally biased.

7. The INT1 pin is configured as "push-pull output forced to GND" (and the internal pull-down disabled) as soon as it is configured with the

interrupt configuration bits in the CTRL2 (11h), MD1_CFG (1Fh), EMB_FUNC_INT1 (0Ah), FSM_INT1 (0Bh), and MLC_INT1 (0Dh)

registers.

IIS2DULPX

Application hints

DS14580 - Rev 1

page 19/106

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