IIS2DULPX datasheet(30/106 Pages) STMICROELECTRONICS

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Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred

per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a target receiver doesn’t

acknowledge the target address (that is, it is not able to receive because it is performing some real-time function)

the data line must be left high by the target. The controller can then abort the transfer. A low to high transition on

the SDA line while the SCL line is high is defined as a stop condition. Each data transfer must be terminated by

the generation of a stop (SP) condition.

In the presented communication format CAK is controller acknowledge and NCAK is no controller acknowledge.

6.2

SPI bus interface

The IIS2DULPX SPI is a bus target. The SPI allows writing to and reading from the registers of the device.

The serial interface interacts with the application using four wires: CS, SPC, SDI, and SDO.

Figure 14. Read and write protocol

SPC

SDI

SDO

AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

AD6

CS enables the serial port and it is controlled by the SPI controller. It goes low at the start of the transmission and

goes back high at the end. SPC is the serial port clock and it is controlled by the SPI controller. It is stopped high

when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. Those

lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC.

Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in the

case of multiple read/write bytes. Bit duration is the time between the two falling edges of SPC. The first bit (bit 0)

starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the

last falling edge of SPC just before the rising edge of CS.

bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is

read. In the latter case, the chip drives SDO at the start of bit 8.

bit 1-7: address AD(6:0). This is the address field of the indexed register.

bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).

bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

In multiple read/write commands additional blocks of 8 clock periods are added. When the CTRL1 (10h)

(IF_ADD_INC) bit is 0, the address used to read/write data remains the same for every block. When the CTRL1

(10h) (IF_ADD_INC) bit is 1, the address used to read/write data is increased at every block.

The function and the behavior of SDI and SDO remain unchanged.

IIS2DULPX

Digital interfaces

DS14580 - Rev 1

page 30/106

IIS2DULPX Datasheet(PDF) 30 Page - STMicroelectronics