IIS2DULPX datasheet(20/106 Pages) STMICROELECTRONICS

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Digital main blocks and embedded low-power features

The IIS2DULPX features the following on-chip functions:

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FIFO data buffering

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100% efficiency with flexible configurations and partitioning

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Possibility to store timestamp

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Event-detection interrupts (fully configurable)

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Free-fall

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Wake-up

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6D/4D orientation

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Single/double/triple-tap detection

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Activity/inactivity recognition

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Stationary/motion detection

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Specific IP blocks (called "embedded functions") with negligible power consumption and high-performance

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Pedometer functions: step detector and step counters

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Tilt

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Significant motion detection

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Finite state machine (FSM)

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Machine learning core (MLC) with exportable features and filters for AI applications

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Adaptive self-configuration (ASC)

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Qvar: electric charge variation detection

5.1

FIFO

The IIS2DULPX embeds 128 slots of 7 bytes each (1 byte TAG + 6 bytes DATA). This allows consistent power

saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can

wake up only when needed and burst the significant data out from the FIFO.

FIFO is designed in order to allow the batching of different kinds of sensors. It is possible to store in FIFO the data

of the accelerometer, temperature and analog hub / Qvar physical sensors and the data of virtual sensors like the

step counter, the MLC features / filters / results and FSM results.

The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG byte that allows

recognizing the meaning of a word in FIFO.

The applications have maximum flexibility in choosing the rate of batching for physical sensors with FIFO

dedicated configurations.

FIFO allows correctly reconstructing the timestamp information for each sensor stored in FIFO. Also, if a change

in the ODR or BDR (batch data rate) configuration is performed, the application can correctly reconstruct the

timestamp and know exactly when the change was applied in a FIFO stream without disabling FIFO batching.

FIFO stores information of the new configuration and timestamp in which the change was applied in the device.

In order to maximize the amount of data collected in FIFO, it is possible to double the slots of FIFO data (from 128

to 256) by writing the FIFO_DEPTH bit to 1 in FIFO_CTRL (15h) with 2x depth mode. When this mode is enabled,

the most significant 8 bits for each acceleration data are stored in FIFO. Each FIFO data word contains data of

two consecutive ODRs, the actual and the previous one.

In high-resolution batch mode, accelerometer and temperature (and analog hub / Qvar) data are stored in FIFO in

12-bit format at the ODR rate.

In 2x depth batch mode, each FIFO word contains two accelerometer data in 8-bit format at the ODR/2 rate.

It is possible to avoid storing the temperature/AH/Qvar data in FIFO by setting the XL_ONLY_FIFO bit in

FIFO_WTM (16h) register to 1. In this case, the accelerometer data are stored in FIFO as 16-bit format at the

ODR rate.

IIS2DULPX

Digital main blocks and embedded low-power features

DS14580 - Rev 1

page 20/106

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