IIS2DULPX datasheet(29/106 Pages) STMICROELECTRONICS

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6.1.1

I²C operation

The transaction on the bus is started through a start (ST) signal. A start condition is defined as a high to low

transition on the data line while the SCL line is held high. After this has been transmitted by the controller, the bus

is considered busy. The next byte of data transmitted after the start condition contains the address of the target in

the first 7 bits and the eighth bit tells whether the controller is receiving data from the target or transmitting data to

the target. When an address is sent, each device in the system compares the first seven bits after a start

condition with its address. If they match, the device considers itself addressed by the controller.

The target address (TAD) associated to the IIS2DULPX is 001100xb where the x bit is modified by the TA0/SDO

pin in order to modify the device address. If the TA0/SDO pin is connected to the supply voltage, the address is

0011001b, otherwise if the TA0/SDO pin is connected to ground, the address is 0011000b. This solution permits

to connect and address two different accelerometers to the same I²C lines.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge

pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the

acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each

byte of data received.

The I²C embedded inside the IIS2DULPX behaves like a target device and the following protocol must be adhered

to. After the start condition (ST) a target address is sent. Once a target acknowledge (TAK) has been returned, an

8-bit subaddress (SUB) is transmitted: the 7 LSb represents the actual register address while the CTRL1 (10h)

(IF_ADD_INC) bit defines the address increment.

The target address is completed with a read/write bit. If the bit is 1 (read), a repeated start (SR) condition must be

issued after the two subaddress bytes. If the bit is 0 (write) the controller transmits to the target with direction

unchanged. Table 13 explains how the TAD+read/write bit pattern is composed, listing all the possible

configurations.

Table 13. TAD+read/write patterns

Command

TAD[6:1]

TAD[0] = TA0

R/W

TAD+R/W

Read

001100

00110001 (31h)

Write

001100

00110000 (30h)

Read

001100

00110011 (33h)

Write

001100

00110010 (32h)

Table 14. Transfer when controller is writing one byte to target

Controller

TAD+W

SUB

DATA

Target

TAK

Table 15. Transfer when controller is writing multiple bytes to target

Controller

TAD+W

SUB

DATA

Target

TAK

Table 16. Transfer when controller is receiving (reading) one byte of data from target

Controller

TAD+W

SUB

TAD+R

NCAK

Target

TAK

DATA

Table 17. Transfer when controller is receiving (reading) multiple bytes of data from target

Controller

TAD+W

SUB

TAD+R

CAK

NCAK

Target

TAK

DATA

IIS2DULPX

Digital interfaces

DS14580 - Rev 1

page 29/106

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