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TMP86CS25ADFG Datasheet(PDF) 88 Page - Toshiba Semiconductor |
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TMP86CS25ADFG Datasheet(HTML) 88 Page - Toshiba Semiconductor |
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88 / 194 page  Page 78 8. 18-Bit Timer/Counter (TC1) 8.3 Function TMP86CS25ADFG Figure 8-1 Timing chart for timer mode 8.3.2 Event Counter mode It is a mode to count up at the falling edge of the ECIN pin input. When using this mode, set TC1CR1<TC1CK> to the external clock. The countents of TREG1A are compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared. Counting up resumes for ECIN pin input edge each after the counter is cleared. The maximum applied frequency is fc/24 [Hz] in NORMAL 1/2 or IDLE 1/2 mode and fs/24[Hz] in SLOW or SLEEP mode . Two or more machine cycles are required for both the “H” and “L” levels of the pulse width. Figure 8-2 Event counter mode timing chart 1 0 2 3 4 n 0 1 n-1 2 3 4 5 6 n TREG1A Internal clock Up counter Command Start Match detect Counter clear INTTC1 interrupt 1 0 2 2 n-1 n 0 1 n TREG1A ECIN pin input Up counter Start Match Detect Counter clear INTTC1 interrupt |
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