0.0V

0.0 mV

VnFGD

VSD(TST)

ûVSD(TST)

0.0V

0.0 mV

VGATE

VSD(REV)

ûVSD(REV)

VSD(REG)

LM5051

www.ti.com

SNVS702D – OCTOBER 2011 – REVISED MARCH 2013

Electrical Characteristics (continued)

Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the operating junction temperature (TJ)

range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical

values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless

otherwise stated all conditions and measurements are referenced to device pin 7 (INP/VSS), and the following conditions

apply: VLINE= 48.0V, VINN= -150 mV, VOFF= 0.0V, CGATE= 47 nF, CVCC= 0.1 µF, and TJ= 25°C.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

FET Test Comparator

VOFF = 5.0V

FET Test Threshold Voltage

VSD(TST)

VINN/VSS going negative from

-360

-260

-183

mV

VINP - VINN

VINP until nFGD pin goes Hi-Z

VOFF = 5.0V

VINN going positve from

ΔVSD(TST)

FET Test Threshold Voltage Hysteresis

-

6.5

-

mV

VSDT(ST) until nFGD pin goes

Lo-Z

nFGD Pin

nFGD Output Low Voltage

VOFF = 5V

nFGDVOL

-

285

450

mV

nFGD Output = On

InFGD = 1mA Sinking

nFGD Output Leakage Current

VOFF = 0V

nFGDIOL

-

0.01

0.7

µA

nFGD Output = Off

VnFGD = 5.0V

Figure 4. VSD(REV) Threshold Definitions

Figure 5. VSD(TST) Threshold Definitions

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