RD / WR

ANC / CTRL

ADDR

DATA

DATA

ADDR

ADDR

DATA

AD[7:0]

WRITE

EXTERNAL BUS MUST

RELEASE

INTERNAL BUS WILL

RELEASE

ACLK

READ

READ

AD[9:8]

AD[9]

AD[8]

DRIVEN

REC'D

DRIVEN

REC'D

DRIVEN

DRIVEN

AD[9]

AD[8]

AD[8]

AD[9]

AD[8]

AD[9:8]

LMH0031

SNLS218A – JANUARY 2006 – REVISED APRIL 2013

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immediately following the rising edge of ACLK or when the address signal is removed. For optimum system

timing, the signals driving the address to the port should be removed immediately after the address is clocked

into the port and before or simultaneously with the falling edge of ACLK at the end of that address cycle. Output

data remains stable until the next rising edge of ACLK and may be written into external devices at any time after

the removal of the address signal. This second clock resets the port from drive to receive and readies the port for

another access cycle.

Example: Read the Full-field Flags via the AD port.

1. Set ANC/CTRL to a logic-low.

2. Set RD/WR to a logic-high.

3. Present 001h to AD[9:0] as the register address.

4. Toggle ACLK.

5. Release the bus driving the AD port.

6. Read the data present on the AD port. The Full-field Flags are bits AD[4:0].

7. Toggle ACLK to release the AD port.

Figure 4 shows the sequence of clock and control signals for writing control data to the ancillary/control data port.

The control data write mode is similar to the read mode. Control data write mode is invoked by making the

ANC/CTRL input low and the RD/WR input low. The 8-bit address of the control register set to be accessed is

input to the port on bits AD[7:0]. When a control register write address is being written to the port, AD[9:8] must

be driven as 00b (0XXh, where XX are AD[7:0]). The address is captured on the rising edge of ACLK. The

address data is removed on the falling edge of ACLK. Next, the control data is presented to the port bits AD[7:0]

and written into the selected register on the next rising edge of ACLK. When control data is being written to the

port, AD[9:8] must be driven as 11b (3XXh, where XX are AD[7:0]). Control data written into the registers may

be read out non-destructively in most cases.

Example: Setup (without enabling) the TPG Mode via the AD port using the 1125 line, 30 frame, 74.25MHz,

interlaced component (SMPTE 274M) colour bars as test pattern. The TPG may be enabled after setup using the

Multi-function I/O port or by the control registers.

1. Set ANC/CTRL to a logic-low.

2. Set RD/WR to a logic-low.

3. Present 00Dh to AD[9:0] as the Test 0 register address.

4. Toggle ACLK.

5. Present 327h to AD[9:0] as the register data.

6. Toggle ACLK.

Figure 3. Control Data Read Timing (2 read and 1 write cycle shown)

14

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