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LMH0031VS/NOPB Datasheet(PDF) 21 Page - Texas Instruments |
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LMH0031VS/NOPB Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 39 page  LMH0031 www.ti.com SNLS218A – JANUARY 2006 – REVISED APRIL 2013 Table 2. Control Register Bit Assignments (continued) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ANC 1 (register address 05h) ANC ID(7) ANC ID(6) ANC ID(5) ANC ID(4) ANC ID(3) ANC ID(2) ANC ID(1) ANC ID(0) ANC 2 (register address 06h) ANC ID(15) ANC ID(14) ANC ID(13) ANC ID(12) ANC ID(11) ANC ID(10) ANC ID(9) ANC ID(8) ANC 3 (register address 07h) ANC MASK(7) ANC MASK(6) ANC MASK(5) ANC MASK(4) ANC MASK(3) ANC MASK(2) ANC MASK(1) ANC MASK(0) ANC 4 (register address 08h) ANC ANC ANC ANC MASK(15) ANC MASK(14) ANC MASK(13) ANC MASK(9) ANC MASK(8) MASK(12) MASK(11) MASK(10) ANC 5 (register address 17h) FIFO EXTRACT FIFO CLOCK FULL MSG FIFO FLUSH MSG FLUSH reserved reserved MSG TRACK ENABLE ENABLE AVAILABLE STATIC STATIC ANC 6 (register address 18h) ANC FIFO SHORT MSG ANC PARITY reserved reserved reserved reserved VANC 90% FULL DETECT MASK FORMAT 0 (register address 0Bh) FRAMING FORMAT FORMAT FORMAT FORMAT FORMAT SD ONLY HD ONLY MODE SET(4) SET(3) SET(2) SET(1) SET(0) FORMAT 1 (register address 0Ch) F V H FORMAT(4) FORMAT(3) FORMAT(2) FORMAT(1) FORMAT(0) TEST 0 (register address 0Dh) TEST TEST TEST TEST TEST TEST PATTERN PASS/FAIL TPG ENABLE PATTERN PATTERN PATTERN PATTERN PATTERN SELECT(5) SELECT(4) SELECT(3) SELECT(2) SELECT(1) SELECT(0) VIDEO INFO 0 (register address 0Eh) VERT. DE- DE-DITHER VPG FILTER LOCK FRAMING DITHER EAV SAV NSP ENABLE ENABLE DETECT ENABLE ENABLE VIDEO CONTROL 0 (register address 55h) EXTERNAL SYNC DETECT LSB CLIP DE-Scramble reserved reserved NRZI ENABLE reserved VCLK ENABLE ENABLE ENABLE REFERENCE CLOCK (register address 67h) reserved reserved reserved reserved reserved INT_OSC EN CLK EN reserved MULTI-FUNCTION I/O BUS PIN CONFIGURATION I/O PIN 0 CONFIG (register address 0Fh) reserved reserved PIN 0 SEL[5] PIN 0 SEL[4] PIN 0 SEL[3] PIN 0 SEL[2] PIN 0 SEL[1] PIN 0 SEL[0] I/O PIN 1 CONFIG (register address 10h) reserved reserved PIN 1 SEL[5] PIN 1 SEL[4] PIN 1 SEL[3] PIN 1 SEL[2] PIN 1 SEL[1] PIN 1 SEL[0] I/O PIN 2 CONFIG (register address 11h) reserved reserved PIN 2 SEL[5] PIN 2 SEL[4] PIN 2 SEL[3] PIN 2 SEL[2] PIN 2 SEL[1] PIN 2 SEL[0] I/O PIN 3 CONFIG (register address 12h) reserved reserved PIN 3 SEL[5] PIN 3 SEL[4] PIN 3 SEL[3] PIN 3 SEL[2] PIN 3 SEL[1] PIN 3 SEL[0] I/O PIN 4 CONFIG (register address 13h) reserved reserved PIN 4 SEL[5] PIN 4 SEL[4] PIN 4 SEL[3] PIN 4 SEL[2] PIN 4 SEL[1] PIN 4 SEL[0] I/P PIN 5 CONFIG (register address 14h) reserved reserved PIN 5 SEL[5] PIN 5 SEL[4] PIN 5 SEL[3] PIN 5 SEL[2] PIN 5 SEL[1] PIN 5 SEL[0] I/O PIN 6 CONFIG (register address 15h) reserved reserved PIN 6 SEL[5] PIN 6 SEL[4] PIN 6 SEL[3] PIN 6 SEL[2] PIN 6 SEL[1] PIN 6 SEL[0] I/O PIN 7 CONFIG (register address 16h) reserved reserved PIN 7 SEL[5] PIN 7 SEL[4] PIN 7 SEL[3] PIN 7 SEL[2] PIN 7 SEL[1] PIN 7 SEL[0] Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: LMH0031 |
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