PIC16F18344-ISLASHP datasheet(53/489 Pages) MICROCHIP

53 / 489 page

Bank 31 — only accessible from Debug Executive, unless otherwise specified

CPU CORE REGISTERS; see Table 4-2 for specifics

F8Ch to

FE3h

—

— —

Unimplemented

—

FE4h(2)

STATUS_SHAD

—

—Z

---- -xxx

---- -uuu

FE5h(2)

WREG_SHAD

Working Register Normal (Non-ICD) Shadow

xxxx xxxx

uuuu uuuu

FE6h(2)

BSR_SHAD

—

Bank Select Register Normal (Non-ICD) Shadow

---x xxxx

---u uuuu

FE7h(2)

PCLATH_SHAD

—

Program Counter Latch High Register Normal (Non-ICD) Shadow

-xxx xxxx

-uuu uuuu

FE8h(2)

FSR0L_SHAD

Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow

xxxx xxxx

uuuu uuuu

FE9h(2)

FSR0H_SHAD

Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow

xxxx xxxx

uuuu uuuu

FEAh(2)

FSR1L_SHAD

Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow

xxxx xxxx

uuuu uuuu

FEBh(2)

FSR1H_SHAD

Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow

xxxx xxxx

uuuu uuuu

FECh

—

Unimplemented

—

FEDh(2)

STKPTR

—

Current Stack pointer

---x xxxx

---1 1111

FEEh(2)

TOSL

Top of Stack Low byte

xxxx xxxx

FEFh(2)

TOSH

—

Top of Stack High byte

-xxx xxxx

TABLE 4-4:

SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

Resets

Legend:

= unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note

Only on PIC16F18324/18344.

PIC16F18344-I/P Datasheet(PDF) 53 Page - Microchip Technology

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