PIC16F18344-ISLASHP datasheet(71/489 Pages) MICROCHIP

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DS40001800C-page 71

PIC16(L)F18324/18344

6.3

Low-Power Brown-out Reset

(LPBOR)(PIC16LF18324/18344

Devices Only)

The Low-Power Brown-Out Reset (LPBOR) circuit

provides alternative protection against Brown-out

conditions for the PIC16LF18324/18344 devices.

When VDD falls below the LPBOR threshold, the device

is held in Reset. When this occurs, the BOR bit of the

PCON0 register is cleared to indicate that a Brown-out

Reset occurred. The BOR bit will be cleared when

either the BOR or the LPBOR circuitry detects a BOR

condition. The LPBOR feature can be used with or

without BOR enabled.

When used while BOR is enabled, the LPBOR can be

used as a secondary protection circuit in case the BOR

circuit fails to detect the BOR condition. Additionally,

when BOR is enabled except while in Sleep

(BOREN<1:0> = 10), the LPBOR circuit will hold the

device in Reset while VDD is lower than the LPBOR

threshold, and will also re-arm the POR. (See

Table 35-11 for LPBOR Reset voltage levels).

When used without BOR enabled, the LPBOR circuit

provides a single Reset trip point with the benefit of

reduced current consumption.

6.3.1

ENABLING LPBOR

The LPBOR is controlled by the LPBOR bit of

Configuration Words. When the device is erased, the

LPBOR module defaults to disabled.

6.3.1.1

LPBOR Module Output

The output of the LPBOR module is a signal indicating

whether or not a Reset is to be asserted. This signal is

OR’d together with the Reset signal of the BOR

module to provide the generic BOR signal, which goes

to the PCON0 register and to the power control block.

6.4

MCLR

The MCLR is an optional external input that can reset

the device. The MCLR function is controlled by the

MCLRE bit of Configuration Words and the LVP bit of

Configuration Words (Table 6-2).

6.4.1

MCLR ENABLED

When MCLR is enabled and the pin is held low, the

device is held in Reset. The MCLR pin is connected to

VDD through an internal weak pull-up.

The device has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

6.4.2

MCLR DISABLED

When MCLR is disabled, the pin functions as a general

purpose input and the internal weak pull-up is under

software

control.

See

Section 12.2

“PORTA

Registers”

for more information.

6.5

Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware

does not issue a CLRWDT instruction within the time-out

period. The TO and PD bits in the STATUS register as

well as the RWDT bit in the PCON0 register, are

changed to indicate the WDT Reset. See Section 10.0

“Watchdog Timer (WDT)”

for more information.

6.6

RESET

Instruction

A RESET instruction will cause a device Reset. The RI

bit in the PCON0 register will be set to ‘0’. See Table 6-4

for default conditions after a RESET instruction has

occurred.

6.7

Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or

Underflows. The STKOVF or STKUNF bits of the

PCON0 register indicate the Reset condition. These

Resets are enabled by setting the STVREN bit in

Configuration Words. See Section 4.4 “Stack” for more

information.

6.8

Programming Mode Exit

Upon exit of Programming mode, the device will

behave as if a device Reset had just occurred.

6.9

Power-up Timer

The Power-up Timer provides a nominal 64 ms

time-out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.

The PWRT delay allows additional time for the VDD to

rise to an acceptable level. The Power-up Timer is

enabled by clearing the PWRTE bit in Configuration

Words.

The Power-up Timer starts after the release of the POR

and BOR.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

TABLE 6-2:

MCLR CONFIGURATION

MCLRE

LVP

MCLR

Disabled

Enabled

Note:

A Reset does not drive the MCLR pin low.

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