ADC32RF44IRMPR datasheet(51/135 Pages) TI2

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SYNCb

SYSREF

LMFC Clock

LMFC Boundary

xxx

Transmit Data

K28.5

ILA

DATA

Multi

Frame

Code Group

Synchronization

Initial Lane Alignment

Data Transmission

Test Patterns

Transport Layer

Scrambler

1+x

14+x15

Comma Characters

Initial Lane

Alignment

Link Layer

JESD204B Block

D[3:0]

SYNCB

Frame Data

Mapping

8b, 10b

Encoding

ADC32RF44

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SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017

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Device Functional Modes (continued)

The JESD204B transmitter block consists of the transport layer, the data scrambler, and the link layer, as shown

in Figure 111. The transport layer maps the ADC output data into the selected JESD204B frame data format and

manages if the ADC output data or test patterns are transmitted. The link layer performs the 8b, 10b data

encoding as well as the synchronization and initial lane alignment using the SYNC input signal. Optionally, data

from the transport layer can be scrambled.

Figure 111. JESD Digital Block Implementation

9.4.2.1 JESD204B Initial Lane Alignment (ILA)

The receiving device starts the initial lane alignment process by deasserting the SYNCB signal. The SYNCB

signal can be issued using the SYNCB input pins or by setting the proper SPI bits. When a logic low is detected

on the SYNCB input, the ADC32RF44 starts transmitting comma (K28.5) characters to establish the code group

synchronization, as shown in Figure 112.

When synchronization completes, the receiving device reasserts the SYNCB signal and the ADC32RF44 starts

the initial lane alignment sequence with the next local multiframe clock boundary. The ADC32RF44 transmits

four multiframes, each containing K frames (K is SPI programmable). Each of the multiframes contains the frame

start and end symbols. The second multiframe also contains the JESD204 link configuration data.

Figure 112. JESD Internal Timing Information

ADC32RF44IRMPR Datasheet(PDF) 51 Page - Texas Instruments

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