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ADC32RF44IRMPR Datasheet(PDF) 58 Page - Texas Instruments |
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ADC32RF44IRMPR Datasheet(HTML) 58 Page - Texas Instruments |
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58 / 135 page  tSLOADS R/W A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDIN SCLK SEN RESET A11 A10 A9 A8 A7 A6 M P CH Register Address [11:0] Register Data [7:0] tDH tDSU tSLOADH tSCLK 58 ADC32RF44 SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017 www.ti.com Product Folder Links: ADC32RF44 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 9.4.3 Serial Interface The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins. Serially shifting bits into the device is enabled when SEN is low. SDIN serial data are latched at every SCLK rising edge when SEN is active (low), as shown in Figure 113. The interface can function with SCLK frequencies from 20 MHz down to low speeds (of a few hertz) and also with a non-50% SCLK duty cycle, as shown in Table 26. The SPI access uses 24 bits consisting of eight register data bits, 12 register address bits, and four special bits to distinguish between read/write, page and register, and individual channel access, as described in Table 27. Figure 113. SPI Timing Diagram Table 26. SPI Timing Information MIN TYP MAX UNIT fSCLK SCLK frequency (equal to 1 / tSCLK) 1 20 MHz tSLOADS SEN to SCLK setup time 50 ns tSLOADH SCLK to SEN hold time 50 ns tDSU SDIN setup time 10 ns tDH SDIN hold time 10 ns tSDOUT Delay between SCLK falling edge to SDOUT 10 ns |
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