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SPSB081 Datasheet(PDF) 47 Page - STMicroelectronics |
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SPSB081 Datasheet(HTML) 47 Page - STMicroelectronics |
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47 / 137 page  4.2.2.7 Data-out payload The payload (data bytes 1 to 3) is the data transferred from the slave device with every SPI communication to the master device. The payload always follows the OpCode and the address bits of the actual shifted in data (in-frame-response). 4.3 Address definition Table 15. Device application access Operating code OC1 OC0 0 0 0 1 1 0 Table 16. RAM address range RAM address Description Access 3FH Configuration register R/W 38H Status register 8 R/C … … - 32H Status register 2 R/C 31H Status register 1 R/C … … - 22H Control register 34 R/W 18H Control register 24 R/W … … - 02H Control register 2 R/W 01H Control register 1 R/W 00H Reserved - Table 17. Device information read access Operating code OC1 OC0 1 1 Table 18. ROM address range ROM address Description Access 3FH <Advanced Op.> W 3EH <GSB options> R … - - 20H <SPI CPHA test> R 16H <WD bit pos. 4> R SPSB081 Address definition DS14048 - Rev 3 page 47/137 |
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