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SPSB081 Datasheet(PDF) 58 Page - STMicroelectronics |
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SPSB081 Datasheet(HTML) 58 Page - STMicroelectronics |
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58 / 137 page ![]() Symbol Parameter Condition Min Typ Max Unit Item VDP1 Drop-out voltage ILOAD = 150 mA, VSREG = 5 V and VSREG= 3.55 V(1) (V1 = 3.3 V); T = 25 °C - V 0.35 0.5 C.008 ICCmax1 Short circuit output current (to GND) Current limitation 450 750 1100 mA C.010 Cload1(2) Load capacitor1 Ceramic (±20%) 1(3) - 10(1) µF C.011 tTSD V1 deactivation time after thermal shut-down Tested by scan - 1.5 - sec C.012 ICMP_ris(4) Current comp. rising threshold (to GND) Rising current ICMP_SET = 0 1 4 7 mA C.013 Rising current ICMP_SET = 1 6 12 18 C.047 ICMP_fal(4) Current comp. falling threshold (to GND) Falling current ICMP_SET = 0 0.4 2.8 4.2 mA C.014 Falling current ICMP_SET = 1 4 10 15 C.048 ICMP_hys(4) Current comp. hysteresis ICMP_SET = 0 1.2 mA C.015 ICMP_SET = 1 1 2 4 C.049 V1fail V1 fail threshold V1 forced (V1 = 5 V) - 2 3 V C.016 V1 forced (V1 = 3.3 V) - 1.3 2 C.050 tOV1filter1 V1 overvoltage filter time1 Tested by scan - 20 30 µs C.051 tOV1filter2 V1 overvoltage filter time2 Tested by scan - 20 30 µs C.052 tV1fail V1 fail filter time Tested by scan 6 13 20 µs C.017 tV1short V1 short filter time Tested by scan 2 4 5 ms C.018 tV1FS V1 fail-safe filter time Tested by scan 1.43 2 2.06 ms C.019 tV1off V1 deactivation time after 8 consecutive WD failures Tested by scan - 200 270 ms C.020 1. Below 3.55 V, the POR VSREG can be activated and there is a device reset. 2. Guaranteed by design. 3. Nominal capacitor value required for stability of the regulator. Tested with 1 μF ceramic (±20%). Capacitor must be located close to the regulator output pin. A 2.2 μF capacitor value is recommended to minimize the DPI (Direct power injection) stress in the application. 4. In active mode, V1 regulator is switched to high accuracy mode. Below the Icmp threshold, regulator switches in any case to nominal accuracy mode (same behavior applies also in case of high current). 5.4 Voltage regulator V2 The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V ≤ VS ≤ 28 V; 4.5 V ≤ VSREG ≤ 28 V; TJ = from -40 °C to 150 °C, unless otherwise specified. The same parameter values in both 5 V and 3.3 V conditions apply unless otherwise specified. Table 31. Voltage regulator V2 Symbol Parameter Condition Min Typ Max Unit Item V2 Output voltage including line and load regulation VSREG ≥ 6.5 V - 5.0 - V C.053 - 3.3 - C.054 V2high_acc Output voltage tolerance High accuracy mode ILOAD = 100 μA to 50 mA, (active mode) VSREG = 13.5 V -2.5 - +2.5 % C.055 V2100mA Output voltage tolerance (50… 100 mA) ILOAD = 100 mA, VSREG = 13.5 V -3 - +3 % C.056 SPSB081 Voltage regulator V2 DS14048 - Rev 3 page 58/137 |
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