SPSB081 datasheet(51/137 Pages) STMICROELECTRONICS

51 / 137 page

Figure 30. Window watchdog operation

The watchdog trigger bit location is defined by the <WD bit pos. X> registers.

Table 25. WD bit position

Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WB1 WB0

WBA5

WBA4

WBA3

WBA2

WBA1

WBA0

Defines the register addresses of the WD trigger bits

WBA5

WBA4

WBA3

WBA2

WBA1

WBA0

Defines the stop address of the address range (previous <WD bit pos. X> is a WB = ‘01’)

The consecutive <WD bitpos. X> has to be a WB = ‘11’

WBP4

WBP3

WBP2

WBP1

WBP0

Defines the binary bit position of the WD trigger bit within the register

<WD bit pos 1>: 41H; watchdog trigger bit located at address 01H (CR1).

<WD bit pos 2>: C0H; watchdog trigger bit location is bit0.

<WD bit pos 3>: 7FH; watchdog trigger bit located at address 3FH (config register).

<WD bit pos 4>: C0H; watchdog trigger bit location is bit0.

4.3.2

Device application registers (RAM)

The device application registers are all registers accessible using OpCode ‘00’, ‘01’ and ‘10’. The functions of

these registers are defined in the device specification.

4.4

Protocol failure detection

To realize a protocol, which covers certain fail-safe requirements a basic set of failure detection mechanisms are

implemented.

SPSB081

Protocol failure detection

DS14048 - Rev 3

page 51/137

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