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MSP430F14X Datasheet(PDF) 30 Page - Texas Instruments

Part # MSP430F14X
Description  MSP430F14x, MSP430F14x1, MSP430F13x Mixed-Signal Microcontrollers
PDF  88 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

MSP430F14X Datasheet(HTML) 30 Page - Texas Instruments

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MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
www.ti.com
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Product Folder Links: MSP430F149 MSP430F148 MSP430F147 MSP430F1491 MSP430F1481 MSP430F1471
MSP430F135 MSP430F133
Specifications
Copyright © 2000–2018, Texas Instruments Incorporated
(1)
Not production tested, limits verified by design
(2)
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
(3)
Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2
n+1) × (R
S + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
5.26 12-Bit ADC, Timing Parameters
over recommended operating supply voltage and free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fADC12CLK
ADC clock frequency
For specified performance of ADC12 linearity
parameters
2.2 V, 3 V
0.45
5
6.3
MHz
fADC12OSC
Internal ADC12 oscillator
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V, 3 V
3.7
6.3
MHz
tCONVERT
Conversion time
CVREF+ ≥ 5 µF, internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz
2.2 V, 3 V
2.06
3.51
µs
External fADC12CLK from ACLK, MCLK or
SMCLK, ADC12SSEL
≠ 0
13 ×
1/fADC12CLK
tADC12ON
Turn-on settling time of
the ADC(1)
See (2)
100
ns
tSample
Sampling time(1)
RS = 400 Ω, RI = 1000 Ω, CI = 30 pF,
τ = [RS + RI] × CI
(3)
3 V
1220
ns
2.2 V
1400
5.27 12-Bit ADC, Linearity Parameters
over recommended operating supply voltage and free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EI
Integral
linearity error
1.4 V
≤ (VVeREF+ – VVREF-/VeREF-)min ≤ 1.6 V
2.2 V, 3 V
±2
LSB
1.6 V < (VVeREF+ – VVREF-/VeREF-)min ≤ VAVCC
±1.7
ED
Differential
linearity error
(VVeREF+ – VVREF-/VeREF-)min ≤ (VVeREF+ – VVREF-/VeREF-),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
±1
LSB
EO
Offset error
(VVeREF+ – VVREF-/VeREF-)min ≤ (VVeREF+ – VVREF-/VeREF-),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
±2
±4
LSB
EG
Gain error
(VVeREF+ – VVREF-/VeREF-)min ≤ (VVeREF+ – VVREF-/VeREF-),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
±1.1
±2
LSB
ET
Total unadjusted
error
(VVeREF+ – VVREF-/VeREF-)min ≤ (VVeREF+ – VVREF-/VeREF-),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
±2
±5
LSB



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